Semiconductor device
An object of the present disclosure is to provide a semiconductor device capable of lowering the threshold voltage without deteriorating the RBSOA tolerance and manufacturing variation. According to the present disclosure, the semiconductor device includes a drift layer of a first conductivity type, a carrier store layer of the first conductivity type, a base layer of a second conductivity type, an emitter layer of the first conductivity type provided on the first main surface side of the base layer, an active trench provided so as to extend through the emitter layer, the base layer, and the carrier store layer and reach the drift layer, a gate insulating film, a gate electrode, and a collector layer of the second conductivity type provided on a second main surface side of the drift layer, in which peak concentration of impurities in the base layer is 1.0E17 cm −3 or higher.
1. A semiconductor device comprising:
a drift layer of a first conductivity type;
a carrier store layer of the first conductivity type provided on a first main surface side of the drift layer;
a base layer of a second conductivity type provided on the first main surface side of the carrier store layer;
an emitter layer of the first conductivity type provided on the first main surface side of the base layer;
a trench provided so as to extend through the emitter layer, the base layer, and the carrier store layer and reach the drift layer;
a gate insulating film having a thickness of 60 nm or less provided on an inner wall of the trench;
a gate electrode embedded in the trench through the gate insulating film; and
a collector layer of the second conductivity type provided on a second main surface side of the drift layer, wherein
peak concentration of impurities in the base layer is 1.0E17 cm −3 or higher, and
the peak concentration of impurities in the base layer and the thickness of the gate insulating film result in a threshold voltage of 3V or less.
2. The semiconductor device according to claim 1 , wherein
the gate insulating film has a thickness of 40 nm or less.
3. The semiconductor device according to claim 1 , wherein
the base layer has a thickness of 1.5 μm or less which is defined by a distance from a boundary between the emitter layer and the base layer to a boundary between the base layer and the carrier store layer.
4. The semiconductor device according to claim 1 , wherein
minimum concentration of impurities in the base layer is 1.5 times or higher than the impurity concentration in the drift layer.
5. The semiconductor device according to claim 1 , further comprising:
a plurality of dummy trenches provided so as to extend through the emitter layer, the base layer, and the carrier store layer and reach the drift layer;
a dummy gate insulating film provided on an inner wall of each of the plurality of dummy trenches;
a dummy gate electrode embedded in each of the plurality of dummy trenches through the dummy gate insulating film; and
an interlayer insulating film provided on an upper portion of a mesa region between the plurality of dummy trenches, wherein
potential in the mesa region is floating.
6. The semiconductor device according to claim 1 , further comprising:
a power semiconductor region and a diode region, wherein
the power semiconductor region includes at least the drift layer, the carrier store layer, the base layer, the emitter layer, the trench, the gate insulating film, and the collector layer,
the diode region includes
an anode layer of the second conductivity type provided on the first main surface side of the drift layer,
a diode trench provided so as to extend through the anode layer and reach the drift layer, and
a cathode layer of the first conductivity type provided on the second main surface side of the drift layer, and
a distance between an end portion of the cathode layer and an end portion of the emitter layer is 0 or more.
7. The semiconductor device according to claim 1 , wherein
the gate electrode and a shield electrode are embedded in the trench through the gate insulating film,
a bottom portion of the gate electrode is located at a position corresponding to the carrier store layer in a cross-sectional view, and
an upper portion of the shield electrode is located at a position corresponding to the carrier store layer and a bottom portion thereof is located at a position corresponding to the drift layer in a cross-sectional view.
8. The semiconductor device according to claim 1 , wherein
in a plan view, the emitter layer and contact layers of the second conductivity type extend orthogonally to the trench which is linearly arranged, and also are alternately arranged, and
a width in a direction orthogonal to an extending direction of the emitter layer is 1.0 μm or less.
9. The semiconductor device according to claim 1 , wherein
a minimum concentration of impurities in the base layer is approximately 1.0E15 cm −3 .
10. The semiconductor device according to claim 1 , wherein
a concentration of impurities in a region of the base layer, that includes more than half the base layer, is 1E16 cm −3 or more.