Semiconductor device with field effect transistors and method of fabricating the same
Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.
1. A semiconductor device, comprising:
a substrate with an active pattern;
a gate electrode crossing the active pattern;
a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof;
a contact electrically connected to the source/drain region, the contact including a lower portion in the recess region;
a metal silicide layer in a lower region of the recess region, the metal silicide layer being between the source/drain region and the contact; and
a spacer in an upper region of the recess region, the spacer being between the source/drain region and the contact and spaced apart from the metal silicide layer,
wherein a bottom of the spacer and the metal silicide layer have a non-overlapping relationship,
wherein the bottom of the spacer is positioned at a lower level than a top of the source/drain region, and
wherein the metal silicide layer and the spacer define an inner sidewall of the recess region, the inner sidewall having a staircase profile.
2. The device as claimed in claim 1 , wherein the source/drain region has a top surface higher than a bottom surface of the contact.
3. The device as claimed in claim 1 , wherein a bottom surface of the contact is spaced apart from a bottom surface of the recess region with the metal silicide layer therebetween.
4. The device as claimed in claim 1 , wherein a bottom surface of the spacer is positioned at a higher level than a bottom surface of the contact.
5. The device as claimed in claim 1 , wherein a bottom surface of the spacer is positioned at substantially the same level as a bottom surface of the contact.
6. The device as claimed in claim 1 , wherein the metal silicide layer is in contact with a bottom surface of the contact and with a bottom surface of the spacer.
7. The device as claimed in claim 1 , wherein the lower portion of the contact includes:
a first portion adjacent to an upper region of the recess region, and
a second portion adjacent to the lower region of the recess region, the first portion having a width greater than that of the second portion.
8. The device as claimed in claim 1 , wherein the contact includes a conductive pillar and a barrier layer enclosing the conductive pillar.
9. The device as claimed in claim 1 , further comprising an interlayered insulating layer covering the active pattern, the source/drain region, and the gate electrode,
wherein the contact is connected to the source/drain region through the interlayered insulating layer.
10. The device as claimed in claim 1 , further comprising device isolation layers on the substrate to define the active pattern, the source/drain region and the upper portion of the active pattern protruding upwardly between the device isolation layers.
11. The device as claimed in claim 10 , further comprising:
gate spacers on sidewalls of the gate electrode; and
a gate dielectric layer between the gate electrode and the gate spacers, and between the gate electrode and the active pattern,
wherein the gate spacers and the gate dielectric layer extend along the gate electrode.
12. A semiconductor device, comprising:
device isolation layers on a substrate to define an active pattern;
a gate electrode crossing the active pattern;
a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof;
a contact electrically connected to the source/drain region, the contact including a lower portion in the recess region; and
a metal silicide layer at a lower region of the recess region, the metal silicide layer being between the source/drain region and the contact,
wherein, when viewed in a cross-sectional view along a direction perpendicular to a longitudinal direction of the gate electrode, an inner sidewall of the recess region has a staircase profile, a portion of the inner sidewall of the recess region directly contacting the contact and the metal silicide layer at a boundary between the contact and the metal silicide layer, and
wherein at least a portion of the contact extends into a portion of the recess with a smallest width.
13. The device as claimed in claim 12 , further comprising a spacer at an upper region of the recess region, the spacer being between the source/drain region and the contact, wherein the contact and the spacer are arranged to trace a same profile as the staircase profile of the recess region.
14. The device as claimed in claim 12 , wherein the lower portion of the contact includes:
a first portion adjacent to an upper region of the recess region, and
a second portion adjacent to a lower region of the recess region, the first portion and the second portion having a same profile as the staircase profile of the recess region.
15. A semiconductor device, comprising:
a substrate with an active pattern;
a source/drain region in a portion of the active pattern, the source/drain region defining a recess region at an upper region thereof;
a contact electrically connected to the source/drain region, the contact including a lower portion in the recess region; and
a spacer covering a sidewall of the contact, the spacer including a lower portion between the source/drain region and the lower portion of the contact, a bottom surface of the spacer being positioned at a higher level than a bottom surface of the recess region and at a lower level than a top of the source/drain region,
wherein the contact extends into the recess region beyond the bottom surface of the spacer, such that a bottom surface of the contact is positioned at a lower level than the bottom surface of the spacer.
16. The device as claimed in claim 15 , further comprising an interlayered insulating layer covering the active pattern and the source/drain region, the contact penetrating the interlayered insulating layer, and an upper portion of the spacer being between the interlayered insulating layer and an upper portion of the contact.
17. The device as claimed in claim 15 , wherein a width of a portion of the recess region contacting a bottom of the spacer is larger than a width of a lowermost surface of the recess region.
18. The device as claimed in claim 15 , further comprising a metal silicide layer on a bottom of the recess, the contact extending into the metal silicide layer.