Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET)

1. A method of forming a Fin field-effect transistor (FinFET) semiconductor structure comprising:

performing an angled ion implantation process at a predetermined angle on a first sidewall of a fin to cause damage to the first sidewall of the fin; and

removing the damage caused to the first sidewall of the fin.

2. The method of claim 1 , wherein the angled implantation process comprises an Xe ion implantation process, and the predetermined angle is between 30 degrees and 80 degrees.

3. The method of claim 1 , further comprising depositing spacer material on the first sidewall and the second sidewall of the fin.

4. The method of claim 1 , wherein a total on resistance (R on ) of the FinFET is decreased and an extension resistance (R ext ) of the FinFET increases.

5. The method of claim 3 , further comprising:

removing the spacer material from the first sidewall of the fin; and

performing a selective epitaxy process on the first sidewall of the fin.

6. The method of claim 3 , wherein the damage is caused to the spacer material on the first sidewall of the fin.

7. The method of claim 3 , further comprising:

removing the spacer material from the second sidewall of the fin; and

selectively growing an epitaxy layer on the second sidewall of the fin.

8. The method of claim 6 , wherein removing the damage comprises etching damaged spacer material using a hydrofluoric acid (HF) solution.

9. The method of claim 4 , wherein the FinFET is a p-type field-effect transistor (pFET).

10. The method of claim 9 , wherein the pFET is part of a static random access memory (SRAM) cell.

11. A semiconductor device, comprising:

a Fin field-effect transistor (FinFET), the FinFET including:

a channel region; and

a fin including a first portion of a first sidewall comprising remaining spacer material from removal of spacer material from a second portion of the first sidewall damaged by an angled ion implantation process.

12. The semiconductor device of claim 11 , wherein:

the FinFET further includes:

gate; and

a source/drain region; and

the angled ion implantation process damages the spacer material on the second portion of the first sidewall, which is removed from the first sidewall.

13. The semiconductor of claim 12 , wherein the fin further includes spacer material on a first portion of a second sidewall, the first portion of the second sidewall comprising remaining spacer material from removal of spacer material from a second portion of the second sidewall caused by the angled ion implantation process that damages the spacer material on the second portion of the second sidewall, which is removed from the second sidewall.

14. The semiconductor of claim 12 , wherein the FinFET is a p-type field-effect transistor (pFET) that is part of a static random access memory (SRAM) cell.

15. A method of forming a semiconductor device, comprising:

forming a first fin and a second fin of a Fin field-effect transistor (FinFET) on a substrate, wherein the FinFET is a p-type field-effect transistor (pFET);

performing angled ion implantation at a predetermined angle on a first side of the first fin and a first side of the second fin; and

removing damage caused to the first side of the first fin and to the first side of the second fin.

16. The method of claim 15 , wherein removing the damage comprises etching the damage caused by the ion implantation from the first side of the first fin and the first side of the second fin.

17. The method of claim 16 , further comprising:

selectively growing an epitaxy layer on the first side of the first fin and the first side of the second fin, such that a total on resistance (R on ) of the FinFET is decreased and an extension resistance (R ext ) of the FinFET increases.

18. The method of claim 17 , further comprising:

forming a spacer layer on the first fin and the second fin;

forming a masking on the spacer layer on the substrate except for a portion with the first fin and the second fin; and

removing the masking;

wherein the ion implantation comprises Xe ion implantation, and the predetermined angle is between 30 degrees and 80 degrees.

19. The method of claim 15 , wherein the pFET is part of a static random access memory (SRAM) cell, and etching the damage is based on using hydrofluoric acid (HF).

20. The method of claim 18 , wherein forming the masking on the spacer layer on the substrate except for the portion with the first fin and the second fin further comprises performing copolymer block lithography on a first group of pull-down device fins and a second group of pull-down device fins.