Techniques enabling low power states for a communications port
Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.
1. An apparatus, comprising:
processor circuitry; and
power management logic for execution on the processor circuitry to determine when a communications port of the apparatus is in a first low power state, determine that a device coupled to the communications port entered a low power state based on detection of a de-assertion of a clock request signal on a uni-directional clock request signal link from the device to the communications port, disable squelch controller circuitry based upon detection of the de-assertion of the clock request signal, and enable a second low power state for the communications port based on the determination that the device entered the low power state, the second low power state to use less power than the first low power state.
2. The apparatus of claim 1 , the power management logic to determine that a latency tolerance requirement of the device is greater than a power gating exit latency threshold, and to enable a third low power state for the communications port based on the determination.
3. The apparatus of claim 2 , the third low power state to use less power than both the second low power state and the first low power state.
4. The apparatus of claim 1 , the power management logic to enable second low power state for the communications port when the squelch controller circuitry is disabled.
5. The apparatus of claim 2 , the power management logic to determine when the latency tolerance requirement of the device is greater than the power gating exit latency threshold based on a received latency tolerance report from the coupled device and power gate an analog front end circuitry when the latency tolerance requirement is greater than the power gating exit latency threshold.
6. The apparatus of claim 5 , the power management logic to power gate the analog front end circuitry when the latency tolerance requirement is greater than the power gating exit latency threshold, the clock request signal on the uni-directional clock request signal link is de-asserted and squelch controller circuitry is disabled.
7. The apparatus of claim 5 , the power management logic to enable the third low power state for the communications port is enabled when the analog front end circuitry is power gated.
8. An article comprising a non-transitory computer-readable storage medium containing a plurality of instructions that when executed enable a processor circuit to:
determine when a communications port is in a first low power state;
determine that a coupled device entered a low power state based on detection of a de-assertion of a clock request signal on a uni-directional clock request signal link from the coupled device to the communication port;
disable squelch controller circuitry based upon detection of the de-assertion of the clock request signal; and
enable a second low power state based on the determination that the device is entering the low power state, the second low power state to use less power than the first low power state.
9. The article of claim 8 , comprising instructions that when executed enable the processing circuit to determine that a latency tolerance requirement of the device is greater than a power gating exit latency threshold, and to enable a third low power state based on the determination.
10. The article of claim 9 , the third low power state to use less power than both the second low power state and the first low power state.
11. The article of claim 8 , comprising instructions that when executed enable the processing circuit to enable the second low power state when the squelch controller circuitry is disabled.
12. The article of claim 8 , comprising instructions that when executed enable the processing circuit to:
determine that a latency tolerance requirement of the device is greater than the power gating exit latency threshold based on a received latency tolerance report; and
power gate analog front end circuitry when the latency tolerance requirement is greater than the power gating exit latency threshold.
13. The article of claim 8 , comprising instructions that when executed enable the processing circuit to power gate analog front end circuitry when a latency tolerance requirement is greater than a power gating exit latency threshold, the clock request signal on the uni-directional clock request signal link is de-asserted and squelch circuitry is disabled.
14. The article of claim 13 , comprising instructions that when executed enable the processing circuit to enable a third low power state when the analog front end circuitry is power gated.
15. A computer-implemented method, comprising:
determining when a communications port is in a first low power state;
determining that a coupled device entered a low power state based on detection of a de-assertion of a clock request signal on a uni-directional clock request signal link from the coupled device to the communication port;
disabling squelch controller circuitry based upon detection of the de-assertion of the clock request signal; and
enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.
16. The computer-implemented method of claim 15 , comprising:
determining that a latency tolerance requirement of the device is greater than a power gating exit latency threshold, and to enable a third low power state based on the determination.
17. The computer-implemented method of claim 16 , the third low power state to use less power than both the second low power state and the first low power state.
18. The computer: implemented method of claim 15 , comprising enabling the second low power state when the squelch controller circuitry is disabled.
19. The computer-implemented method of claim 15 , comprising:
determining that a latency tolerance requirement of the device is greater than the power gating exit latency threshold based on a received latency tolerance report; and
power gating analog front end circuitry when the latency tolerance is greater than the power gating exit latency threshold.
20. The computer-implemented method of claim 15 , comprising:
power gating analog front end circuitry when a latency tolerance requirement is greater than a power gating exit latency threshold, the clock request signal on the uni-directional clock request signal link is de-asserted and squelch circuitry is disabled.
21. The computer-implemented method of claim 20 , comprising enabling a third low power state when the analog front end circuitry is power gated.