Managing power states in a data storage device
The disclosure relates in some aspects to managing power states in a data storage device. A data storage device may receive a request from a host device to transition to a particular power state. Such a request may be used to cause the data storage device to transition to a corresponding internal power state. In some scenarios, the host device might not support the same internal power states that are supported by the data storage device. In this case, the data storage device may transition to an internal power state that is lower than the internal power state supported by the host device in conjunction with the request.
1 . A data storage device, comprising:
a non-volatile memory array;
a peripheral component interconnect (PCI) interface; and
at least one processor coupled to the non-volatile memory array and the PCI interface and configured to:
receive, via the PCI interface, a request from a host device to enter a D3 power state associated with a first reduced power mode where device power is not removed;
responsive to the receipt of the request, determine whether the host device supports an L1.2 link state associated with a second reduced power mode where link common mode voltages are not required to be maintained; and
set a first power state of the data storage device to a non-operational power state responsive to the receipt of the request and a determination that the host device does not support the L1.2 link state.
2 . The data storage device of claim 1 , wherein the first power state is a non-volatile memory express (NVMe) power state.
3 . The data storage device of claim 2 , wherein the non-operational power state is an NVMe PS5 power state.
4 . The data storage device of claim 1 , wherein the PCI-D3 power state is a PCI express (PCIe) D3hot power state.
5 . The data storage device of claim 4 , wherein the at least one processor is further configured to:
enter the PCIe D3hot power state responsive to the receipt of the request and the determination that the host device does not support the L1.2 link state.
6 . The data storage device of claim 1 , wherein the at least one processor is further configured to:
set a power management control and status register (PMCSR) to indicate the L1.2 link state responsive to the receipt of the request and the determination that the host device does not support the L1.2 link state.
7 . The data storage device of claim 1 , wherein the at least one processor is further configured to:
configure a wake-up circuit for electrical idle broken (EIB) signal detection responsive to the receipt of the request and the determination that the host device does not support the L1.2 link state.
8 . The data storage device of claim 7 , wherein the at least one processor is further configured to:
set the first power state of the data storage device to an operational power state responsive to a detection of an EIB signal.
9 . The data storage device of claim 1 , wherein the at least one processor is further configured to:
configure at least one component of the data storage device to transition from a first component power state to a second component power state that is associated with lower power consumption than the first component power state responsive to the receipt of the request and the determination that the host device does not support the L1.2 link state.
10 . The data storage device of claim 9 , wherein the at least one processor is further configured to:
configure the at least one component to transition from the second component power state to the first component power state responsive to a detection of an electrical idle broken (EIB) signal.
11 . The data storage device of claim 1 , wherein the at least one processor is further configured to:
power off at least one of a processing core, a memory circuit, or a phase-locked loop (PLL) responsive to the receipt of the request and the determination that the host device does not support the L1.2 link state.
12 . The data storage device of claim 11 , wherein, to power off the at least one of the processing core, the memory circuit, or the PLL, the at least one processor is further configured to:
set or clear at least one bit in at least one register that controls the at least one of the processing core, the memory circuit, or the PLL.
13 . The data storage device of claim 11 , wherein the at least one processor is further configured to:
power on the at least one of the processing core, the memory circuit, or the phase-locked loop (PLL) responsive to a detection of an electrical idle broken (EIB) signal.
14 . A method for controlling at least one power state of a data storage device, comprising:
receiving a request from a host device to enter a D3 power state associated with a first reduced power mode where device power is not removed;
responsive to the receipt of the request, determining whether the host device supports an L1.2 link state associated with a second reduced power mode where link common mode voltages are not required to be maintained; and
setting a first power state of the data storage device to a non-operational power state responsive to the receipt of the request and a determination that the host device does not support the L1.2 link state.
15 . The method of claim 14 , wherein:
the first power state is a non-volatile memory express (NVMe) power state; and
the D3 power state is a peripheral component interconnect express (PCIe) D3hot power state.
16 . The method of claim 14 , further comprising:
monitoring for an electrical idle broken (EIB) signal responsive to the receiving of the request and the determination that the host device does not support the L1.2 link state.
17 . The method of claim 16 , further comprising:
setting the first power state of the data storage device to an operational power state responsive to a detection of the EIB signal.
18 . The method of claim 16 , further comprising:
entering a D0 power state responsive to a detection of the EIB signal.
19 . The method of claim 14 , further comprising:
suspending at least one data storage thread responsive to the receiving of the request and the determination that the host device does not support the L1.2 link state.
20 . A data storage device, comprising:
a peripheral component interconnect (PCI) interface;
means for receiving, via the PCI interface, a request from a host device to enter a D 3 power state associated with a first reduced power mode where device power is not removed;
means for determining, responsive to the receipt of the request, whether the host device supports an L1.2 link state associated with a second reduced power mode where link common mode voltages are not required to be maintained; and
means for setting a first power state of the data storage device to a non-operational power state responsive to the receipt of the request and a determination that the host device does not support the L1.2 link state.