Fabrication of radio-frequency devices with amplifier voltage limiting features
Fabrication of a wireless device involves providing a packaging substrate configured to receive a plurality of components, mounting a radio-frequency module on the packaging substrate, the radio-frequency module including a power amplifier including a bipolar transistor having collector, emitter, base and sub-collector regions, the radio-frequency module further including a conductive via positioned within 35 μm of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, and electrically connecting the radio-frequency module to the packaging substrate using a plurality of connectors.
1. A method of fabricating a wireless device comprising:
providing a packaging substrate configured to receive a plurality of components;
mounting a radio-frequency module on the packaging substrate, the radio-frequency module including a bipolar transistor formed on a semiconductor substrate, the bipolar transistor having collector, emitter, base, and sub-collector regions, the radio-frequency module further including an epitaxial layer of low-resistivity substrate formed at a top surface of the semiconductor substrate, a conductive via positioned within 35 μm of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, a low-resistivity well implanted at the top surface of the semiconductor substrate, and a high-resistivity implant region implanted at the top surface of the semiconductor substrate between the low-resistivity well and the conductive via; and
electrically connecting the radio-frequency module to the packaging substrate using a plurality of connectors.
2. The method of claim 1 wherein the conductive via is positioned a distance of between approximately 15-25 μm from the sub-collector region of the bipolar transistor.
3. The method of claim 1 wherein the conductive via is disposed a distance of approximately 20 μm from the sub-collector region of the bipolar transistor.
4. The method of claim 1 wherein the conductive via is formed a distance of between approximately 10-15 μm from the sub-collector region of the bipolar transistor.
5. A method of fabricating a radio-frequency module comprising:
providing a packaging substrate configured to receive a plurality of components;
mounting a semiconductor die on the packaging substrate, the semiconductor die including a bipolar transistor having collector, emitter, base, and sub-collector regions, the semiconductor die further including an epitaxial layer of low-resistivity substrate formed at a top surface of the semiconductor substrate, a through-silicon via positioned within 35μm of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, a low-resistivity well implanted at the top surface of the semiconductor substrate, and a high-resistivity implant region implanted at the top surface of the semiconductor substrate between the low-resistivity well and the through-silicon via; and
electrically connecting the semiconductor die to the packaging substrate.
6. The method of claim 5 wherein the through-silicon via is disposed a distance of between approximately 15-25 μm from the sub-collector region of the bipolar transistor.
7. The method of claim 5 wherein the through-silicon via is disposed a distance of approximately 20 μm from the sub-collector region of the bipolar transistor.
8. The method of claim 5 wherein the through-silicon via is disposed a distance of between approximately 10-15 μm from the sub-collector region of the bipolar transistor.
9. The method of claim 5 wherein the voltage limit level is between approximately 4-9 volts.
10. The method of claim 5 wherein the bipolar transistor has a silicon-germanium alloy base.
11. A method of fabricating a semiconductor die comprising:
providing a semiconductor substrate;
forming a bipolar transistor over the semiconductor substrate, the bipolar transistor having collector, emitter, base, and sub-collector regions;
forming an epitaxial layer of low-resistivity substrate at a top surface of the semiconductor substrate;
forming a conductive via at least partially through the semiconductor substrate within 35 μm of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level;
implanting a low resistivity well at the top surface of the semiconductor substrate; and
implanting a high-resistivity implant region at the top surface of the semiconductor substrate between the low-resistivity well and the conductive via.
12. The method of claim 11 wherein the conductive via is formed a distance of between approximately 15-25 μm from the sub-collector region of the bipolar transistor.
13. The method of claim 11 wherein the conductive via is formed a distance of approximately 20 μm from the sub-collector region of the bipolar transistor.
14. The method of claim 11 wherein the conductive via is formed a distance of between approximately 10-15 μm from the sub-collector region of the bipolar transistor.
15. The method of claim 11 wherein the voltage limit level is between approximately 4-9 volts.
16. The method of claim 11 wherein said forming the bipolar transistor involves forming the bipolar transistor on a silicon-germanium alloy base.
17. The method of claim 11 wherein the semiconductor substrate has a resistivity greater than 50 Ohm*cm.
18. The method of claim 17 wherein the high-resistivity implant region has a resistivity value greater than 500 Ohm*cm.
19. The method of claim 17 wherein the high-resistivity implant region has a resistivity of approximately 1 kOhm*cm.