Vertical high voltage semiconductor apparatus and fabrication method of vertical high voltage semiconductor apparatus
A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.
1. A fabrication method of a vertical high voltage semiconductor apparatus comprising:
forming on a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate;
forming selectively on a surface of the first semiconductor layer and using an ion implantation method, a second semiconductor layer of a second conductivity type having an impurity concentration higher than that of the first semiconductor layer;
forming a base layer of the second conductivity type on the first semiconductor layer and the second semiconductor layer, using an epitaxial growth method;
selectively implanting impurities into the base layer using the ion implantation method, to make implanted portions of the base layer into an N-counter layer of the first conductivity type, the N-counter layer penetrating the base layer from a surface and reaching the first semiconductor layer, and then, selectively implanting impurities into the base layer using the ion implantation method, to make implanted portions of the base layer into a first conductivity type source region, the first conductivity type source region being formed on the base layer; and
forming a gate electrode layer disposed through a gate insulating film in at least a portion at an exposed portion of a surface of the base layer between the source region and the N-counter layer, the exposed portion of the surface of the base layer having second conductivity type, wherein
the forming of the second semiconductor layer includes forming the second semiconductor layer such that portions of the second semiconductor layer are directly connected with each other in regions directly beneath the N-counter layers.