Low noise CMOS image sensor by stack architecture

1. A pixel circuit for use in a high dynamic range (HDR) image sensor, comprising:

a photodiode disposed in a first semiconductor wafer, the photodiode adapted to photogenerate charge carriers in response to incident light during a single exposure of a single image capture of the HDR image sensor;

a floating diffusion disposed in the first semiconductor wafer and coupled to receive the charge carriers photogenerated in the photodiode;

a transfer transistor disposed in the first semiconductor wafer and coupled between the photodiode and the floating diffusion, wherein the transfer transistor is adapted to be switched on to transfer the charge carriers photogenerated in the photodiode to the floating diffusion;

an in-pixel capacitor disposed in a second semiconductor wafer, wherein the first semiconductor wafer is stacked with and coupled to the second semiconductor wafer; and

a dual floating diffusion (DFD) transistor disposed in the first semiconductor wafer and coupled between the floating diffusion and the in-pixel capacitor, wherein the DFD transistor is coupled to be enabled or disabled in response to a DFD signal such that the in-pixel capacitor is selectively coupled to the floating diffusion through the DFD transistor in response to the DFD signal, wherein the floating diffusion is set to low conversion gain in response to the in-pixel capacitor being coupled to the floating diffusion, and wherein the floating diffusion is set to high conversion gain in response to the in-pixel capacitor being decoupled from the floating diffusion.

2. The pixel circuit of claim 1 , further comprising an amplifier transistor disposed in the first semiconductor wafer, wherein the amplifier transistor has a gate terminal coupled to the floating diffusion to generate an output signal of the pixel circuit.

3. The pixel circuit of claim 2 , further comprising a row select transistor disposed in the second semiconductor wafer and coupled to the amplifier transistor to selectively couple the output signal of the pixel circuit to an output bitline in the second semiconductor wafer.

4. The pixel circuit of claim 3 , further comprising a first via coupled between the first and second semiconductor wafers, and coupled between the row select transistor and the amplifier transistor.

5. The pixel circuit of claim 1 further comprising a reset transistor disposed in the second semiconductor wafer and coupled to the in-pixel capacitor in the second semiconductor wafer and the DFD transistor in the first semiconductor wafer, wherein the reset transistor is coupled to selectively reset the floating diffusion and the photodiode in response to a reset signal.

6. The pixel circuit of claim 5 wherein the DFD transistor is selectively switched on with the reset transistor to reset the floating diffusion and the photodiode.

7. The pixel circuit of claim 5 , further comprising a second via coupled between the first and second semiconductor wafers, and coupled between the reset transistor and the DFD transistor.

8. The pixel circuit of claim 1 , wherein the in-pixel capacitor is terminated to ground.

9. The pixel circuit of claim 1 , wherein the in-pixel capacitor is coupled to a pulse drive signal.

10. The pixel circuit of claim 1 , wherein the floating diffusion is capacitively coupled to a boost signal.

11. A high dynamic range (HDR) imaging sensor system, comprising:

a pixel array of pixel circuits, wherein each one of the pixel circuits includes:

a photodiode disposed in a first semiconductor wafer, the photodiode adapted to photogenerate charge carriers in response to incident light during a single exposure of a single image capture of the HDR imaging sensor system;

a floating diffusion disposed in the first semiconductor wafer and coupled to receive the charge carriers photogenerated in the photodiode;

a transfer transistor disposed in the first semiconductor wafer and coupled between the photodiode and the floating diffusion, wherein the transfer transistor is adapted to be switched on to transfer the charge carriers photogenerated in the photodiode to the floating diffusion;

an in-pixel capacitor disposed in a second semiconductor wafer, wherein the first semiconductor wafer is stacked with and coupled to the second semiconductor wafer; and

a dual floating diffusion (DFD) transistor disposed in the first semiconductor wafer and coupled between the floating diffusion and the in-pixel capacitor, wherein the DFD transistor is coupled to be enabled or disabled in response to a DFD signal such that the in-pixel capacitor is selectively coupled to the floating diffusion through the DFD transistor in response to the DFD signal, wherein the floating diffusion is set to low conversion gain in response to the in-pixel capacitor being coupled to the floating diffusion, and wherein the floating diffusion is set to high conversion gain in response to the in-pixel capacitor being decoupled from the floating diffusion;

control circuitry coupled to the pixel array to control operation of the pixel array; and

readout circuitry coupled to the pixel array to readout image data from the plurality of pixels.

12. The HDR imaging sensor system of claim 11 , further comprising function logic coupled to the readout circuitry to store the image data from each one of the pixel circuits.

13. The HDR imaging sensor system of claim 11 , wherein each one of the pixel circuits further comprises an amplifier transistor disposed in the first semiconductor wafer, wherein the amplifier transistor has a gate terminal coupled to the floating diffusion to generate an output signal of the pixel circuit.

14. The HDR imaging sensor system of claim 13 , wherein each one of the pixel circuits further comprises a row select transistor disposed in the second semiconductor wafer and coupled to the amplifier transistor to selectively couple the output signal of the pixel circuit to an output bitline in the second semiconductor wafer.

15. The HDR imaging sensor system of claim 14 , wherein each one of the pixel circuits further comprises a first via coupled between the first and second semiconductor wafers, and coupled between the row select transistor and the amplifier transistor.

16. The HDR imaging sensor system of claim 11 , wherein each one of the pixel circuits further comprises a reset transistor disposed in the second semiconductor wafer and coupled to the in-pixel capacitor in the second semiconductor wafer and the DFD transistor in the first semiconductor wafer, wherein the reset transistor is coupled to selectively reset the floating diffusion and the photodiode in response to a reset signal.

17. The HDR imaging sensor system of claim 16 , wherein the DFD transistor is selectively switched on with the reset transistor to reset the floating diffusion and the photodiode.

18. The HDR imaging sensor system of claim 16 , wherein each one of the pixel circuits further comprises a second via coupled between the first and second semiconductor wafers, and coupled between the reset transistor and the DFD transistor.

19. The HDR imaging sensor system of claim 11 , wherein the in-pixel capacitor is terminated to ground.

20. The HDR imaging sensor system of claim 11 , wherein the in-pixel capacitor is coupled to a pulse drive signal.

21. The HDR imaging sensor system of claim 11 , wherein the floating diffusion is capacitively coupled to a boost signal.