Interconnect sharing with integrated control for reduced pinout

1. A device comprising:

an external serial interface, at a semiconductor die, including a data terminal, a selection terminal to receive a selection signal that selects the device to communicate via the external serial interface, and a clock terminal to receive a clock signal that indicates when digital information is to be provided to the data terminal;

a buffer of the semiconductor die including an input to receive a secondary signal, and an output to provide the secondary signal to the data terminal;

a digital driver of the semiconductor die including a digital output to provide a signal to the data terminal;

a first storage location of the semiconductor die to have a storage state based upon a stored first select indicator; and

select circuitry of the semiconductor die to selectively 1) provide the secondary signal from the buffer on the external serial interface via the output of the buffer to the data terminal in response to a first state of a storage location in which the stored first select indicator is stored and in response a first state of the selection signal, and 2) provide the signal from the digital driver on the external serial interface via the output of the digital driver to the data terminal in response to a second state of the storage location in response a second state of the selection signal.

2. The device of claim 1 wherein the semiconductor die is configured to receive a serial command over the serial external interface to store the stored first select indicator at the storage location.

3. The device of claim 1 wherein the serial external interface is a Serial Peripheral Interface (SPI).

4. The device of claim 3 wherein the data terminal is a Master In Slave Out (MISO) terminal of the SPI.

5. The device of claim 3 wherein an analog signal is communicated at all times other than during SPI communications.

6. The device of claim 1 further comprising:

an analog-to-digital converter (ADC) having an ADC input to receive the secondary signal, and an output selectively coupled to the input of the digital driver to provide a digital representation of the secondary signal for serial transmission at the data terminal, wherein the secondary signal is an analog signal.

7. The device of claim 6 wherein the device provides validation of the ADC operation by, at a first time, providing the digital representation of the secondary signal for serial transmission at the data terminal and, at a second time, providing the secondary signal as an analog signal to the data terminal for off-chip data conversion and comparison.

8. A method, implemented in an integrated circuit (IC), comprising:

enabling a serial bus by asserting a selection signal;

receiving a serial command on the serial bus over a first interconnect of a plurality of interconnects of the IC;

enabling an analog buffer to drive the first interconnect;

disabling the serial bus by deasserting the selection signal;

driving the first interconnect with a secondary information-carrying signal from the analog buffer in response to the deasserting the selection signal;

reenabling the serial bus by reasserting the selection signal;

discontinuing driving the first interconnect with the secondary information-carrying signal in response to the reasserting the selection signal;

communicating serial data on the serial bus over the first interconnect;

again disabling the serial bus by again deasserting the selection signal; and

again driving the first interconnect with the secondary information-carrying signal in response to the again deasserting the selection signal.

9. The method of claim 8 wherein the enabling the serial bus by asserting the selection signal comprises:

communicating the selection signal over a second interconnect of the plurality of interconnects.

10. The method of claim 8 wherein the receiving the serial command on the serial bus over the first interconnect of the plurality of interconnects of the IC comprises:

receiving the serial command on the serial bus to enable the analog buffer to drive the first interconnect with the secondary information-carrying signal and to select a multiplexer channel of a multiplexer coupled to the analog buffer.

11. The method of claim 8 wherein the serial bus is implemented according to a Serial Peripheral Interface (SPI) and wherein the selection signal is communicated on an active-low chip select bar (CSb) line of the SPI.

12. The method of claim 11 wherein the serial data is communicated on a slave out (SO) line of the SPI.

13. The method of claim 8 further comprising:

receiving a secondary input signal at the analog buffer and at an analog-to-digital converter (ADC), the ADC coupled to the serial bus, and the analog buffer outputting the secondary signal;

performing analog-to-digital conversion of the secondary input signal using the analog-to-digital converter (ADC) to provide a digital representation of the secondary input signal; and

selectively communicating, over the first interconnect, the secondary signal as an analog representation of the secondary input signal and a portion of the serial data as the digital representation of the secondary input signal.

14. The method of claim 13 wherein the selectively communicating, over the first interconnect, the secondary signal as the analog representation of the secondary input signal and the portion of the serial data as the digital representation of the secondary input signal provides redundant communication.

15. An integrated circuit (IC) comprising:

a semiconductor die, the semiconductor die comprising a buffer and a serial interface, the serial interface providing a serial bus, the serial bus comprising a data line and a selection line;

a plurality of interconnects coupled to the semiconductor die, the semiconductor die configured to time multiplex, on a first interconnect of the plurality of interconnects, serial data of the data line when the selection line enables the serial bus and a secondary information-carrying signal of the buffer when the selection line disables the serial bus; and

a package housing the semiconductor die and at least a portion of the plurality of interconnects.

16. The IC of claim 15 wherein a second interconnect of the plurality of interconnects is configured to communicate a selection signal of the selection line.

17. The IC of claim 15 wherein the semiconductor die is configured to receive a serial command over the serial bus to enable the buffer and to select a multiplexer channel of a multiplexer coupled to the buffer.

18. The IC of claim 15 wherein the serial interface is a Serial Peripheral Interface (SPI) and wherein the selection line is an active-low chip select bar (CSb) line, wherein an output of the buffer is enabled to drive the first interconnect when the CSb line is at a high logic level.

19. The IC of claim 18 wherein the data line is a slave out (SO) line.

20. The IC of claim 15 further comprising:

an analog-to-digital converter (ADC) coupled to the serial interface, the ADC having an ADC input to receive a secondary input signal, the buffer configured to receive the secondary input signal, the IC configured to selectively communicate the secondary signal as an analog representation of the secondary input signal and a portion of the serial data as a digital representation of the secondary input signal.