IP Library Granted Patent US 10,236,392
Granted Patent B2
US 10,236,392 · App. 15/952,433 · Granted Mar 19, 2019

Transistor and semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Masayuki Sakakura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/78693H01L27/0688H01L27/092H01L27/1225H01L29/045H01L29/105H01L29/41733H01L29/42384H01L29/78648H01L29/78696H01L21/823807H01L2029/42388
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Quick Facts
Patent No.
US 10,236,392
App. No.
15/952,433
Granted
Mar 19, 2019
Kind
B2
Abstract

A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

Claims (34)

1. A semiconductor device comprising:

a first insulating layer;

a first oxide semiconductor layer over the first insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a second insulating layer over the second oxide semiconductor layer;

a gate electrode provided in an opening in the second insulating layer;

a gate insulating layer provided between the second oxide semiconductor layer and the gate electrode; and

a third oxide semiconductor layer provided between the second oxide semiconductor layer and the gate insulating layer,

wherein in a section of a channel width direction, a bottom surface of the gate electrode has a region which does not overlap with the first oxide semiconductor layer and the second oxide semiconductor layer, and

wherein the region of the bottom surface of the gate electrode is located below a bottom surface of the first oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer overlaps with a protruding portion of the first insulating layer.

3. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer comprises indium.

4. A semiconductor device comprising:

a first insulating layer;

a first oxide semiconductor layer over the first insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a second insulating layer over the second oxide semiconductor layer;

a gate electrode provided in an opening in the second insulating layer; and

a gate insulating layer provided between the second oxide semiconductor layer and the gate electrode,

wherein in a section of a channel width direction, a bottom surface of the gate electrode has a region which does not overlap with the first oxide semiconductor layer and the second oxide semiconductor layer, and

wherein the region of the bottom surface of the gate electrode is located below a bottom surface of the first oxide semiconductor layer.

5. The semiconductor device according to claim 4 , wherein the first oxide semiconductor layer overlaps with a protruding portion of the first insulating layer.

6. The semiconductor device according to claim 4 , wherein the first oxide semiconductor layer comprises indium.

7. A semiconductor device comprising:

a first insulating layer;

a first oxide semiconductor layer over the first insulating layer;

a second insulating layer over the first oxide semiconductor layer;

a gate electrode provided in an opening in the second insulating layer; and

a gate insulating layer provided between the first oxide semiconductor layer and the gate electrode;

a second oxide semiconductor layer provided between the first oxide semiconductor layer and the gate electrode;

wherein in a section of a channel width direction, a bottom surface of the gate electrode has a region which does not overlap with the first oxide semiconductor layer, and

wherein the region of the bottom surface of the gate electrode is located below a bottom surface of the first oxide semiconductor layer.

8. The semiconductor device according to claim 7 , wherein the first oxide semiconductor layer overlaps with a protruding portion of the first insulating layer.

9. The semiconductor device according to claim 7 , wherein the first oxide semiconductor layer comprises indium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2018
From: YAMAZAKI, SHUNPEI; SAKAKURA, MASAYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 046018/0111 →
Priority Claims (1)
JP 2014-069534 · Mar 28, 2014 · national
Continuity (2)
Continuation 14669459 · Mar 26, 2015
Related Publication 20180233601A1 · Aug 16, 2018
Cited By (4)
US 12,199,187 US 12,317,600 US 12,446,302 US 12,563,716