Method and apparatus for generating a multi-level pseudo-random test signal
View Patent ↗The present invention relates to a method for generating multi-level PRBS patterns for testing purposes, wherein the method includes the steps of providing a binary PRBS signal with a binary bit pattern sequence and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output.
1. A method for generating multi-level PRBS patterns, comprising:
providing a binary PRBS signal with a binary bit pattern sequence; and
mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output,
wherein one symbol of a list of symbols is sequentially output each time one or more state machines are triggered by a bit tester configured for triggering a first state machine using a first trigger signal, and for triggering a second state machine using a second trigger signal for each of one or more clock cycles of a clock signal, and
wherein the multilevel output signal is synchronized to the clock signal and transmitted via a transmission channel.
2. The method according to claim 1 , wherein the symbol level is represented by a level of an electrical quantity, particularly of a voltage.
3. The method according to claim 2 , wherein a first state of the bits of the binary bit pattern sequence is associated to a first set of symbols and wherein a second state of the bits of the binary bit pattern sequence is associated to a second set of symbols.
4. The method according to claim 3 , wherein the symbols of the first set of symbols are represented by levels of an electrical quantity having a first sign and the symbols of the second set of symbols are represented by levels of an electrical quantity having a second sign.
5. The method according to claim 4 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.
6. The method according to claim 4 , wherein the multilevel output is a N-PAM output, wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols.
7. The method according to claim 6 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.
8. The method according to claim 3 , wherein the multilevel output is a N-PAM output, wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols.
9. The method according to claim 8 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.
10. The method according to claim 2 , wherein a first state of the bits of the binary bit pattern sequence is associated to a first set of symbols and wherein a second state of the bits of the binary bit pattern sequence is associated to a second set of symbols.
11. The method according to claim 10 , wherein the symbols of the first set of symbols are represented by levels of an electrical quantity having a first sign and the symbols of the second set of symbols are represented by levels of an electrical quantity having a second sign.
12. The method according to claim 11 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.
13. The method according to claim 11 , wherein the multilevel output is a N-PAM output, wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols.
14. The method according to claim 13 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.
15. The method according to claim 10 , wherein the multilevel output is a N-PAM output, wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols.
16. The method according to claim 15 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.
17. An apparatus for generating multi-level PRBS patterns for testing purposes, comprising:
a PRBS generator for providing a binary PRBS signal with a binary bit pattern sequence; and
a mapping unit for mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output,
wherein one symbol of a list of symbols is sequentially output each time one or more state machines are triggered by a bit tester configured for triggering a first state machine using a first trigger signal, and for triggering a second state machine using a second trigger signal for each of one or more clock cycles of a clock signal, and
wherein the multilevel output signal is synchronized to the clock signal and transmitted via a transmission channel.
18. The apparatus according to claim 17 , the apparatus further comprising:
a state machine for each state of the binary PRBS signal,
wherein the triggering of the state machines by the bit tester is dependent on the state of the binary PRBS signal, and
wherein the state machines are configured to output one symbol of a list of symbols sequentially each time they are triggered by the bit tester.
19. The apparatus according to claim 18 , the apparatus further comprising:
a signal combining unit for combining outputs of the state machines to obtain the multilevel output.
20. The apparatus of claim 17 , wherein symbols of a first set of symbols are represented by levels of an electrical quantity having a first sign and symbols of a second set of symbols are represented by levels of an electrical quantity having a second sign.