Methods, systems and apparatus for predicting the way of a set associative cache
A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
1. A method for fetching a cache line of a far taken branch instruction and a cache line of a target of the far taken branch instruction, the method comprising:
determining a hit at a first way of an instruction cache for the far taken branch instruction;
determining a target address from an information cache based on the first way;
determining a second way from a shadow cache tag structure based on the target address; and
fetching the far taken branch instruction from the instruction cache based on the first way and the target of the far taken branch instruction from a shadow cache based on the second way.
2. The method of claim 1 , wherein the information cache stores addresses for targets of far taken branch instructions.
3. The method of claim 1 , wherein the far taken branch instruction is in a first cache line and the target of the far taken branch instruction is in a second cache line.
4. The method of claim 3 , wherein the first cache line and the second cache line are fetched in a same clock cycle.
5. The method of claim 3 , further comprising:
forwarding the first cache line and the second cache line to a scheduler of a processor for execution by one or more execution units.
6. The method of claim 1 , further comprising:
copying targets of one or more far taken branch instructions, including the far taken branch instruction, to the shadow cache.
7. A method for fetching a cache line of a far taken branch instruction and a cache line of a target of the far taken branch instruction, the method comprising:
determining a hit at a first way of an instruction cache for the far taken branch instruction;
determining a second way from a way predictor based on the first way, wherein the way predictor stores predicted ways per way from the instruction cache; and
fetching the far taken branch instruction from the instruction cache based on the first way and the target of the far taken branch instruction from a shadow cache based on the second way.
8. The method of claim 7 , wherein the far taken branch instruction is in a first cache line and the target of the far taken branch instruction is in a second cache line.
9. The method of claim 8 , wherein the first cache line and the second cache line are fetched in a same clock cycle.
10. The method of claim 8 , further comprising:
forwarding the first cache line and the second cache line to a scheduler of a processor for execution by one or more execution units.
11. The method of claim 7 , further comprising:
copying targets of one or more far taken branch instructions, including the far taken branch instruction, to the shadow cache.
12. A processor for fetching a cache line of a far taken branch instruction and a cache line of a target of the far taken branch instruction, the processor comprising:
a cache reader to determine a hit at a first way of an instruction cache for the far taken branch instruction;
a selection component to determine a target address from an information cache based on the first way;
a way selector to determine a second way from a shadow cache tag structure based on the target address; and
a data selector to fetch the far taken branch instruction from the instruction cache based on the first way and the target of the far taken branch instruction from a shadow cache based on the second way.
13. The processor of claim 12 , wherein the information cache stores addresses for targets of far taken branch instructions.
14. The processor of claim 12 , wherein the far taken branch instruction is in a first cache line and the target of the far taken branch instruction is in a second cache line.
15. The processor of claim 14 , wherein the first cache line and the second cache line are fetched in a same clock cycle.
16. The processor of claim 12 , wherein the shadow cache includes targets of one or more far taken branch instructions, including the far taken branch instruction.
17. A processor for fetching a cache line of a far taken branch instruction and a cache line of a target of the far taken branch instruction, the processor comprising:
a cache reader to determine a hit at a first way of an instruction cache for the far taken branch instruction;
a way selector to determine a second way from a way predictor based on the first way, wherein the way predictor stores predicted ways per way from the instruction cache; and
a data selector to fetch the far taken branch instruction from the instruction cache based on the first way and the target of the far taken branch instruction from a shadow cache based on the second way.
18. The processor of claim 17 , wherein the far taken branch instruction is in a first cache line and the target of the far taken branch instruction is in a second cache line.
19. The processor of claim 18 , wherein the first cache line and the second cache line are fetched in a same clock cycle.
20. The processor of claim 18 , further comprising:
one or more execution units for receiving the first cache line and the second cache line in a same clock cycle.