Semiconductor device
In a semiconductor device, a p + back gate region (PBG) is arranged in a main surface (S 1 ) between first and second portions (P 1 , P 2 ) of an n + source region (SR), and arranged on a side closer to an n + drain region (DR) with respect to the n + source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.
1. A semiconductor device having a lateral insulated gate field effect transistor portion, comprising:
a semiconductor substrate having a main surface and an insulating layer formed on said main surface;
a semiconductor layer formed on said insulating layer;
a trench formed to penetrate, in order, the semiconductor layer and the insulating layer, and to reach the semiconductor substrate;
a gate electrode of said insulated gate field effect transistor portion embedded within said trench;
a first impurity region of a first conductivity type, which has first and second portions separated from each other along said trench, in said semiconductor layer, and serves as a source or an emitter;
a second impurity region, which is arranged in said semiconductor layer on a side of the first impurity region opposite to said trench, and serves as a drain of the first conductivity type or a collector of a second conductivity type; and
a back gate region of the second conductivity type, which is arranged in said semiconductor layer between said first and second portions of said first impurity region, and between the second impurity region and said first and second portions of said first impurity region.
2. The semiconductor device according to claim 1 , wherein said back gate region surrounds said first impurity region except for a region where said first impurity region faces said gate electrode.
3. The semiconductor device according to claim 1 , further comprising a conductive layer which is arranged over the semiconductor layer and electrically connected to said first impurity region and said back gate region,
wherein said conductive layer includes:
a first contact which is arranged along said trench to extend over said first and second portions, and connected to said first and second portions and said back gate region, and
a second contact which is arranged over the back gate region along said first contact, on a side of the first contact opposite to said trench, and connected to said back gate region.
4. The semiconductor device according to claim 1 , further comprising a conductive layer which is arranged cover the semiconductor layer and electrically connected to said first impurity region and said back gate region,
wherein said conductive layer includes a third contact which extends in a direction intersecting with said trench, is arranged to extend over said first impurity region and said back gate region, and is connected to said first impurity region and said back gate region.
5. The semiconductor device according to claim 1 , further comprising a silicide layer which is arranged in the semiconductor layer to extend over said first impurity region and said back gate region.
6. The semiconductor device according to claim 1 , further comprising:
a drift region of the first conductivity type which is arranged within said semiconductor layer; and
a first resurf region of the second conductivity type which is in contact with a side of the drift region closest to an upper surface of the semiconductor layer.