Oscillator calibration system
An oscillator system for an integrated circuit includes a first oscillator circuit, a second oscillator circuit, and calibration system. During a sampling routine, the calibration system is used to determine a sampled value based on a comparison of the output of the second oscillator and an external clock signal. The sampled value is stored in a memory. During a calibration routine, the calibration system determines a comparison value based on a comparison of the output of the second oscillator circuit and the output of the first oscillator circuit. The calibration circuit compares the comparison value with the sampled value to generate a tuning value to tune the frequency of the first oscillator circuit.
1. A method for tuning an oscillator circuit, the method comprising:
comparing, with a comparison circuit, an output of a first oscillator circuit with an output of a second oscillator circuit to generate a comparison value, the comparison value based on a frequency of the output of the first oscillator circuit and a frequency of the output of the second oscillator circuit;
comparing the comparison value with a sampled value stored in memory, wherein the sampled value was generated from a comparison with the comparison circuit of an output of the second oscillator circuit with an external clock signal;
providing a tune value to the first oscillator circuit to tune the frequency of the output the first oscillator circuit, the tune value based on the comparing the comparison value with the sampled value.
2. The method of claim 1 wherein the first oscillator circuit is characterized as a relaxation oscillator circuit.
3. The method of claim 1 wherein the second oscillator circuit is characterized as inductor capacitor (LC) based oscillator circuit.
4. The method of claim 1 wherein the second oscillator circuit is characterized as a more frequency stable oscillator circuit than the first oscillator circuit.
5. The method of claim 1 wherein the first oscillator circuit is characterized as a lower power consuming oscillator circuit than the second oscillator circuit.
6. The method of claim 1 further comprising:
dividing down the frequency of the output of the first oscillator circuit prior to the comparing the output of a first oscillator circuit with the output of a second oscillator circuit.
7. The method of claim 1 wherein the comparing the output of a first oscillator circuit with the output of a second oscillator circuit to generate a comparison value includes generating a count with a counter indicative of a number of clock cycles of the output of the second oscillator circuit occurring during a period of time as determined by the output of the first oscillator circuit, wherein comparison value is indicative of the count.
8. The method of claim 7 wherein the sampled value is generated with the counter and is indicative of a number of clock cycles of the output of the second oscillator circuit occurring during a period of time as determined by the external clock signal.
9. The method of claim 1 wherein after the providing a tune value to the first oscillator circuit and the frequency of the output of the first oscillator circuit has been tuned based on the tune value, the method further comprising:
comparing, with the comparison circuit, the output of a first oscillator circuit with the output of a second oscillator circuit to generate a second comparison value, the second comparison value based on the frequency of the output of the first oscillator circuit and the frequency of the output of the second oscillator circuit;
comparing the second comparison value with the sampled value stored in memory;
providing a second tune value to the first oscillator circuit to tune the frequency of the output the first oscillator circuit, the second tune value is based on the comparing the second comparison value with the sampled value.
10. The method of claim 1 wherein after the providing a tune value to the first oscillator circuit to tune the frequency of the output the first oscillator circuit, using the output of the first oscillator circuit as a clock signal for a circuit, wherein the second oscillator circuit is powered down at least during a portion of the using.
11. A circuit for providing a tuned oscillator signal, the circuit comprising:
a first oscillator circuit including an output to provide a first oscillator signal, the first oscillator circuit includes an input to receive a tuning value to tune a frequency of the first oscillator signal;
a second oscillator circuit including an output to provide a second oscillator signal;
a comparison circuit having a first input to receive the first oscillator signal, a second input to receive the second oscillator signal, and a third input to receive an external clock signal, the comparison circuit including an output to provide a comparison value indicative of a comparison of the second oscillator signal with the first oscillator signal and to provide a sampled value indicative of a comparison of the second oscillator signal with the external clock signal;
a memory for storing the sampled value from the comparison circuit;
a tuning circuit that receives the comparison value generated by the comparison circuit, the tuning circuit including an output to provide the tuning value generated by the tuning circuit, the tuning value is based on a comparison of a comparison value and the sampled value from the memory.
12. The circuit of claim 11 wherein the comparison circuit includes a counter, the counter including an output to provide the comparison value indicative of a comparison of the second oscillator signal with the first oscillator signal and to provide the sampled value indicative of a comparison of the second oscillator signal with an external clock signal.
13. The circuit of claim 12 wherein the comparison value is indicative of a count by the counter of a number of clock cycles of the second oscillator signal occurring during a period of time as determined by the first oscillator signal.
14. The circuit of claim 12 wherein the sampled value is indicative of a count by the counter of a number of clock cycles of the second oscillator signal occurring during a period of time as determined by the external clock signal.
15. The circuit of claim 11 wherein the first oscillator circuit is characterized as a relaxation oscillator circuit.
16. The circuit of claim 11 wherein the second oscillator circuit is characterized as inductor capacitor (LC) based oscillator circuit.
17. The circuit of claim 11 wherein the second oscillator circuit is characterized as a more frequency stable oscillator circuit than the first oscillator circuit.
18. The circuit of claim 11 wherein the first oscillator circuit is characterized as a lower power consuming oscillator circuit than the second oscillator circuit.
19. The circuit of claim 11 wherein the comparison circuit further comprises a frequency divider coupled to receive the first oscillator signal and reduce the frequency of the first oscillator circuit for the comparison with the second oscillator signal.
20. A method for tuning an oscillator circuit, the method comprising:
comparing, with a comparison circuit, an output of a first oscillator circuit with an output of a second oscillator circuit to generate a comparison value, the comparison value based on a frequency of the output of the first oscillator circuit and a frequency of the output of the second oscillator circuit;
comparing the comparison value with a value stored in memory, wherein the value stored in memory was generated based on an external clock signal that is not coupled to the comparison circuit, the first oscillator circuit, or the second oscillator circuit during the comparing;
providing a tune value to the first oscillator circuit to tune the frequency of the output the first oscillator circuit, the tune value based on the comparing the comparison value with the value stored in memory.