Wireline transceiver with internal and external clock generation
An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.
1. An integrated circuit device (IC) having functional circuitry driven by a clock signal, the IC comprising onboard clock generation circuitry, the onboard clock generation circuitry comprising:
an input configured to accept a frequency reference signal;
at least one variable loading capacitor coupled to the input for converting the frequency reference signal into a frequency-calibrated clock signal;
calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage, and to generate a derived voltage from the reference voltage, including:
calibration logic circuitry configured to vary a capacitance setting of a selected variable capacitor, and
a comparator configured to change states when the derived voltage passes through the reference voltage, the calibration logic circuitry setting the at least one variable loading capacitor to the capacitance of the selected variable capacitor when the comparator changes state; and
trimming circuitry configured to convert the derived voltage into the frequency-calibrated clock signal.
2. The IC of claim 1 wherein the input configured to accept a frequency reference signal is configured to accept a crystal resonator signal.
3. The IC of claim 1 wherein:
the frequency reference signal is a differential signal;
the at least one variable loading capacitor comprises a respective variable loading capacitor coupled to each respective differential leg of the differential frequency reference signal; and
the calibration circuitry is configured to calibrate both of the respective variable loading capacitors.
4. The IC of claim 1 wherein the selected variable capacitor is one of the at least one variable loading capacitor.
5. The IC of claim 4 wherein:
the frequency reference signal is a differential signal;
the at least one variable loading capacitor comprises a respective variable loading capacitor coupled to each respective differential leg of the differential frequency reference signal; and
the calibration logic circuitry sets each respective variable loading capacitor to the capacitance of the selected variable capacitor when the comparator changes state.
6. The IC of claim 1 wherein the selected variable capacitor is a replica of one of the at least one variable loading capacitor.
7. The IC of claim 6 wherein:
the frequency reference signal is a differential signal;
the at least one variable loading capacitor comprises a respective variable loading capacitor coupled to each respective differential leg of the differential frequency reference signal; and
the calibration logic circuitry sets each respective variable loading capacitor to the capacitance of the replica capacitor when the comparator changes state.
8. The IC of claim 1 wherein the calibration logic circuitry is on the integrated circuit device.
9. The IC of claim 1 wherein the calibration logic circuitry is external to the integrated circuit device.
10. The IC of claim 1 wherein the calibration logic circuitry implements a finite state machine.
11. A method of generating a clock signal onboard an integrated circuit device, the method comprising:
accepting input of a frequency reference signal;
calibrating at least one variable loading capacitor coupled to the frequency reference signal by generating a derived voltage from a reference voltage to charge a selected variable capacitor, including:
varying a capacitance setting of the selected variable capacitor,
comparing magnitude of the derived voltage to the reference voltage, and
setting the at least one variable loading capacitor to the capacitance of the selected variable capacitor when the magnitude of the derived voltage passes through the reference voltage; and
trimming the derived voltage to convert the derived voltage into a frequency-calibrated clock signal using the at least one variable loading capacitor.
12. The method of claim 11 wherein accepting input of a frequency reference signal comprises accepting input of a crystal resonator signal.
13. The method of claim 11 wherein:
accepting input of a frequency reference signal comprises accepting input of a differential frequency reference signal;
trimming the derived voltage to convert the derived voltage into the frequency-calibrated clock signal using the at least one variable loading capacitor comprises using a respective variable loading capacitor coupled to each respective differential leg of the differential frequency reference signal; and
calibrating the at least one variable loading capacitor comprises calibrating both of the respective variable loading capacitors.
14. The method of claim 11 wherein, when the frequency reference signal is a differential signal, setting the at least one variable loading capacitor to the capacitance of the selected variable capacitor when the magnitude of the derived voltage passes through the reference voltage comprises setting capacitance of each one of a respective variable loading capacitor coupled to each respective differential leg of the differential frequency reference signal to the capacitance of the selected variable capacitor when the magnitude of the derived voltage passes through the reference voltage.
15. The method of claim 11 wherein, when the frequency reference signal is a differential signal, setting the at least one variable loading capacitor to the capacitance of the selected variable capacitor when the magnitude of the derived voltage passes through the reference voltage comprises setting a respective variable loading capacitor coupled to each respective differential leg of the differential frequency reference signal to a capacitance of a respective replica of the at least one variable loading capacitor when the magnitude of the derived voltage passes through the reference voltage.