Method of manufacturing isolation structure for semiconductor device
A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
1. A method for manufacturing a semiconductor device, comprising:
forming a first trench to define a first pair of active regions in a substrate;
forming a second trench to define a second pair of active regions in the substrate, wherein the first and the second trenches are electrically connected with each other, wherein the second trench is formed wider than the first trench;
forming a silicon layer over an inner surface of the first trench and over an inner surface of the second trench;
forming a first oxide layer over the silicon layer;
performing an oxidation process of the silicon layer and the first oxide layer to form a second oxide layer, wherein the second oxide layer substantially completely fills the first trench, and
wherein the silicon layer is directly contacted with the inner surface of the first trench and the inner surface of the second trench.
2. The method according to claim 1 , wherein the oxidation process is performed by radical oxidation.
3. The method according to claim 1 , wherein the first oxide layer includes flowable oxide.
4. The method according to claim 1 , wherein the first oxide layer includes hydrogen-containing silicon oxide.
5. The method according to claim 1 , wherein the silicon layer includes amorphous silicon.
6. The method according to claim 1 , further comprising:
forming a nitride layer over the second oxide layer so that the nitride layer fills the second trench;
planarizing the nitride layer and the second oxide layer to form an isolation structure in the first and the second trenches;
forming a gate trench that extends across the isolation structure and the active regions; and
forming a gate dielectric layer over an inner surface of the gate trench.
7. The method according to claim 6 , further comprising:
recessing the isolation structure located under the gate trench to form a fin region.
8. The method according to claim 6 , wherein the for of the gate dielectric layer comprises:
forming a liner silicon layer over the inner surface of the gate trench; and
converting the liner silicon layer into a silicon oxide layer.
9. The method according to claim 6 , wherein the forming of the gate dielectric layer comprises:
forming a silicon nitride layer over the inner surface of the gate trench; and
converting the silicon nitride layer into a silicon oxide layer.
10. The method according to claim 6 , wherein the forming of the gate dielectric layer comprises:
forming a first silicon oxide layer over the inner surface of the gate trench; and
performing an oxidation process to form a second silicon oxide layer between the inner surface of the gate trench and the first silicon oxide layer.
11. The method according to claim 6 , further comprising:
forming a gate layer over the gate dielectric layer to fill the gate trench;
recessing the gate layer to form a gate electrode in the gate trench; and
forming a gate capping layer over the gate electrode and in the gate trench.
12. The method according to claim 11 , further comprising:
forming a bit line coupled to a first contact node of each of the active regions; and
forming a memory element coupled to a second contact node of each of the active regions.
13. A method for manufacturing a semiconductor device, comprising:
forming a first trench to define a first pair of active regions in a substrate;
forming a second trench to define a second pair of active regions in the substrate, wherein the first and the second trenches communicate with each other, wherein the second trench is formed wider than the first trench;
forming a silicon layer over an inner surface of the first trench and over an inner surface of the second trench;
forming a first oxide layer over the silicon layer;
performing an oxidation process of the silicon layer and the first oxide layer to form a second oxide layer, wherein the second oxide layer substantially completely fills the first trench;
forming a nitride layer over the second oxide layer so that the nitride layer fills the second trench;
planarizing the nitride layer and the second oxide layer to form an isolation structure in the first and the second trenches;
forming a gate trench that extends across the isolation structure and the active regions; and
forming a gate dielectric layer over an inner surface of the gate trench.
14. The method according to claim 13 , further comprising:
recessing the isolation structure located under the gate trench to form a fin region.
15. The method according to claim 13 , wherein the forming of the gate dielectric layer comprises:
forming a liner silicon layer over the inner surface of the gate trench; and
converting the liner silicon layer into a silicon oxide layer.
16. The method according to claim 13 , wherein the forming of the gate dielectric layer comprises:
forming a silicon nitride layer over the inner surface of the gate trench; and
converting the silicon nitride layer into a silicon oxide layer.
17. The method according to claim 13 , wherein the forming of the gate dielectric layer comprises:
forming a first silicon oxide layer over the inner surface of the gate trench; and
performing an oxidation process to form a second silicon oxide layer between the inner surface of the gate trench and the first silicon oxide layer.
18. The method according to claim 13 , further comprising:
forming a gate layer over the gate dielectric layer to fill the gate trench;
recessing the gate layer to form a gate electrode in the gate trench; and
forming a gate capping layer over the gate electrode and in the gate trench.
19. The method according to claim 18 , further comprising:
forming a bit line coupled to a first contact node of each of the active regions; and
forming a memory element coupled to a second contact node of each of the active regions.