Front to back resistive random access memory cells
A resistive random-access memory device formed on a semiconductor substrate includes an interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via presents a substantially planar top surface. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer form an aligned stack having edges extending beyond outer edges of the first via. A dielectric barrier layer including a second via is formed over the aligned stack and at least a portion of the chemical-mechanical-polishing stop layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.
1. A resistive random-access memory device formed on a semiconductor substrate and comprising:
an interlayer dielectric formed over the semiconductor substrate and having a first via formed therethrough;
a chemical-mechanical-polishing stop layer formed over the interlayer dielectric, the first via formed through the chemical-mechanical-polishing stop layer;
a lower metal layer formed in the first via, top surfaces of the chemical-mechanical-polishing stop layer and the lower metal layer forming a substantially planar top surface;
a dielectric layer formed over the chemical-mechanical-polishing stop layer and in electrical contact with the lower metal layer;
a barrier metal layer formed over the dielectric layer;
edges of the dielectric layer and the barrier metal layer being in substantial alignment with each other to form an aligned stack disposed directly over the lower metal layer, edges of the aligned stack extending beyond outer edges of the first via;
a dielectric barrier layer formed over the aligned stack and at least a portion of the chemical-mechanical-polishing stop layer, the dielectric barrier layer including a second via formed therethrough communicating with the barrier metal layer; and
an upper metal layer formed in the second via and in electrical contact with the barrier metal layer.
2. The resistive random-access memory device of claim 1 further comprising:
a first barrier metal liner lining side and bottom walls of the first via and in contact with the lower metal layer; and
a second barrier metal liner lining side and bottom walls of the second via and in contact with the upper metal layer.
3. The resistive random-access memory device of claim 1 wherein the barrier metal layer is formed from one of Ta, TaN, Ti, TiN, and W.
4. The resistive random-access memory device of claim 1 wherein the chemical-mechanical-polishing stop layer is formed from one of SiN and SiC.
5. The resistive random-access memory device of claim 1 wherein the dielectric layer is formed from one of GeS, a chalcogenide material, and a glass material.
6. The resistive random-access memory device of claim 1 wherein the dielectric barrier layer is formed from SiN and SiC.
7. The resistive random-access memory device of claim 2 wherein;
the lower metal layer is formed from Cu; and
the first barrier metal liner is formed from one of Ta, TaN, Ti, and TiN.
8. The resistive random-access memory device of claim 7 wherein;
the upper metal layer is formed from Cu; and
the second barrier metal liner is formed from one of Ta, TaN, Ti, and TiN.
9. The resistive random-access memory device of claim 1 further including a second interlayer dielectric separating a first metal interconnect layer and a second metal interconnect layer in an integrated circuit formed on the semiconductor substrate.
10. The resistive random-access memory device of claim 1 wherein:
the lower metal layer includes a seam forming a void; and
the void is filled with a filler material.
11. The resistive random-access memory device of claim 10 wherein the filler material is chosen from one of SiO2, SiN, barrier metals including Ti, Ta, W, TiN, TaN, and a metal.
12. A resistive random-access memory device formed on a semiconductor substrate and comprising:
a first interlayer dielectric formed on the semiconductor substrate and having a first via formed therethrough;
a chemical-mechanical-polishing stop layer formed over the first interlayer dielectric, the first via formed through the chemical-mechanical-polishing stop layer;
a lower metal layer formed in the first via, a top surface of the lower metal layer extending above a top surface of the chemical-mechanical-polishing stop layer;
a first barrier metal layer formed over the chemical-mechanical-polishing stop layer and the top surface of the lower metal layer, the first barrier metal layer in electrical contact with the lower metal layer;
a dielectric layer formed over the first barrier metal layer;
an ion source layer formed over the dielectric layer;
edges of the first barrier metal layer, the dielectric layer, and the ion source layer extending beyond outer edges of the first via;
a second interlayer dielectric formed over the ion source layer extending past the edges of the first barrier metal layer, the dielectric layer, and the ion source layer, the second interlayer dielectric including a second via formed therethrough communicating with the ion source layer; and
an upper metal layer formed in the second via.
13. The resistive random-access memory device of claim 12 further comprising:
a first barrier metal liner lining side and bottom walls of the first via and in contact with the lower metal layer, the first barrier metal liner and the lower metal layer forming a substantially planar top surface;
a dielectric barrier layer formed over the first barrier metal layer, the dielectric layer, and the ion source layer and at least a portion of the chemical-mechanical-polishing stop layer, the dielectric barrier layer including a second via formed therethrough communicating with the barrier metal layer; and
a second barrier metal liner lining side and bottom walls of the second via and in contact with the upper metal layer.
14. The resistive random-access memory device of claim 12 wherein the barrier metal layer is formed from one of Ta, TaN, Ti, TiN, and W.
15. The resistive random-access memory device of claim 12 wherein the chemical-mechanical-polishing stop layer is formed from one of SiN and SiC.
16. The resistive random-access memory device of claim 12 wherein the dielectric layer is formed from one of GeS, a chalcogenide material, and a glass material.
17. The resistive random access memory device of claim 12 wherein the ion source is formed from Ag.
18. The resistive random-access memory device of claim 12 wherein the dielectric barrier layer is formed from SiN and SiC.
19. The resistive random-access memory device of claim 12 wherein;
the lower metal layer is formed from Cu; and
the first barrier metal liner is formed from one of Ta, TaN, Ti, and TiN.
20. The resistive random-access memory device of claim 19 wherein;
the upper metal layer is formed from Cu; and
the second barrier metal liner is formed from one of Ta, TaN, Ti, and TiN.
21. The resistive random-access memory device of claim 12 wherein the second interlayer dielectric is a dielectric layer separating a first metal interconnect layer and a second metal interconnect layer in an integrated circuit formed on the semiconductor substrate.
22. The resistive random-access memory device of claim 12 wherein:
the lower metal layer includes a seam forming a void; and
the void is filled with a filler material.
23. The resistive random-access memory device of claim 22 wherein the filler material is chosen from one of SiO2, SiN, barrier metals including Ti, Ta, W, TiN, TaN, and a metal.