IP Library Granted Patent US 10,262,932
Granted Patent B2
US 10,262,932 · App. 15/441,551 · Granted Apr 16, 2019

Wiring board, and semiconductor device

Inventors: Jun Furuichi (Nagano, JP); Noriyoshi Shimizu (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L23/49838H01L21/486H01L21/4857H01L21/56H01L21/6835H01L23/3121H01L23/49822H01L23/49827H01L23/5383H01L23/5384H01L23/5386H01L24/17H01L24/81H01L21/568H01L23/49894H01L2221/68345H01L2221/68359H01L2224/13014H01L2224/13144H01L2224/16113H01L2224/16238H01L2224/16501H01L2224/81005H01L2224/81193H01L2224/81815H01L2924/014H01L2924/0105H01L2924/01022H01L2924/01024H01L2924/01028H01L2924/01029H01L2924/01046H01L2924/01047H01L2924/01073H01L2924/01079H01L2924/04941H01L2924/04953H01L2924/05432H01L2924/05442H01L2924/0665H01L2924/1432H01L2924/1436H01L2924/1437H01L2924/1438H01L2924/1579H01L2924/15313H01L2924/15747H01L2924/15787H01L2924/18161
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Quick Facts
Patent No.
US 10,262,932
App. No.
15/441,551
Granted
Apr 16, 2019
Kind
B2
Abstract

A wiring board includes: a first wiring structure including: a first insulating layer; a first wiring layer; and a via wiring; a protective insulating layer formed on the lower surface of the first insulating layer to cover a side surface of a lower portion of the first wiring layer; and a second wiring structure having an insulating layer and a wiring layer and formed on the upper surface of the first insulating layer. The upper surface of the first insulating layer and the upper end surface of the via wiring are substantially flush with each other. A wiring density of the second wiring structure is higher than a wiring density of the first wiring structure. The reinforcing material is positioned on a side of the second wiring structure with respect to a center of the first insulating layer in the thickness direction of the first insulating layer.

Claims (44)

1. A wiring board comprising:

a first wiring structure comprising:

a first insulating layer made of an insulating resin including a reinforcing material, wherein the first insulating layer is a single layer;

a recess formed in a lower surface of the first insulating layer;

a first wiring layer having an upper portion filling the recess and a lower portion protruding downward from the lower surface of the first insulating layer; and

a via wiring having an upper end surface exposed from an upper surface of the first insulating layer, wherein the via wiring penetrates the first insulating layer in a thickness direction of the first insulating layer and is directly connected to the upper portion of the first wiring layer;

a protective insulating layer formed on the lower surface of the first insulating layer and covering a side surface of the lower portion of the first wiring layer, wherein an upper surface of the protective insulating layer directly contacts the lower surface of the first insulating layer, and a lower surface of the protective insulating layer is opposite to the upper surface of the protective insulating layer and exposed to an outside of the wiring board; and

a second wiring structure having an insulating layer and a wiring layer and formed on the upper surface of the first insulating layer,

wherein

the upper surface of the first insulating layer and the upper end surface of the via wiring are substantially flush with each other,

a wiring density of the second wiring structure is higher than a wiring density of the first wiring structure,

the reinforcing material is positioned between the second wiring structure and a center of the first insulating layer in the thickness direction of the first insulating layer, and

a portion of a lower surface of the first wiring layer is exposed from the protective insulating layer and serves as an external connection pad.

2. The wiring board of claim 1 , wherein

a volume ratio of the first wiring layer and the via wiring to the first wiring structure is not less than a volume ratio of the wiring layer of the second wiring structure to the second wiring structure.

3. The wiring board of claim 1 , wherein

the reinforcing material is positioned substantially at a center in a thickness direction of a thickness between the lower surface of the first wiring layer and an upper surface of an outermost insulating layer of the second wiring structure.

4. The wiring board of claim 1 , wherein

the first insulating layer further has:

a first resin layer portion covering an upper surface of the reinforcing material; and

a second resin layer portion covering a lower surface of the reinforcing material, and

the first resin layer portion is thinner than the second resin layer portion.

5. The wiring board of claim 4 , wherein

entire surfaces of the reinforcing material are covered with the first resin layer portion and the second resin layer portion.

6. The wiring board of claim 1 , wherein

a plurality of the recess is formed in the lower surface of the first insulating layer,

the first wiring layer has a plurality of wiring patterns and a plurality of dummy patterns which are formed in a region where the plurality of wiring patterns are not formed, each of the plurality of wiring patterns and plurality of dummy patterns having an upper portion filled in a respective recess, and a lower portion protruding downward from the lower surface of the first insulating layer.

7. The wiring board of claim 1 , wherein the upper surface of the protective insulating layer directly contacts a portion of the lower surface of the first wiring layer other than the portion of the lower surface of the first wiring layer exposed from the protective insulating layer.

8. A semiconductor device comprising:

a first wiring structure comprising:

a first insulating layer made of an insulating resin containing a reinforcing material therein, wherein the first insulating layer is a single layer;

a recess formed in a lower surface of the first insulating layer;

a first wiring layer having an upper portion filling the recess and a lower portion protruding downward from the lower surface of the first insulating layer; and

a via wiring having an upper end surface exposed from an upper surface of the first insulating layer, wherein the via wiring penetrates the first insulating layer in a thickness direction of the first insulating layer and is directly connected to the upper portion of the first wiring layer;

a protective insulating layer formed on the lower surface of the first insulating layer and covering a side surface of the lower portion of the first wiring layer, wherein an upper surface of the protective insulating layer directly contacts the lower surface of the first insulating layer, and a lower surface of the protective insulating layer is opposite to the upper surface of the protective insulating layer and exposed to an outside of the wiring board;

a second wiring structure having an insulating layer and a wiring layer and formed on the upper surface of the first insulating layer;

an electronic component which is connected to an uppermost wiring layer of the second wiring structure; and

a sealing resin formed on an upper surface of an uppermost insulating layer of the second wiring structure to seal the electronic component,

wherein

the upper surface of the first insulating layer and the upper end surface of the via wiring are substantially flush with each other,

a wiring density of the second wiring structure is higher than a wiring density of the first wiring structure,

the reinforcing material is positioned between the second wiring structure and a center of the first insulating layer in the thickness direction of the first insulating layer, and

a portion of a lower surface of the first wiring layer is exposed from the protective insulating layer and serves as an external connection pad.

9. The semiconductor device according to claim 8 , wherein the upper surface of the protective insulating layer directly contacts a portion of the lower surface of the first wiring layer other than the portion of the lower surface of the first wiring layer exposed from the protective insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: FURUICHI, JUN; SHIMIZU, NORIYOSHI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 041370/0844 →
Priority Claims (1)
JP 2016-038876 · Mar 1, 2016 · national
Continuity (1)
Related Publication 20170256482A1 · Sep 7, 2017
Cited By (1)
US 12,400,945