IP Library Granted Patent US 12,400,945
Granted Patent B2
US 12,400,945 · App. 18/657,689 · Granted Aug 26, 2025

Electronic device multilevel package substrate for improved electromigration performance

Inventors: Sylvester Ankamah-Kusi (McKinney, TX); Yiqi Tang (Allen, TX); Rajen Manicon Murugan (Dallas, TX); Sreenivasan K. Koduri (Dallas, TX)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L23/49838H01L21/4857H01L23/49822H01L21/6835H01L24/14H01L24/16H01L24/17H01L24/81H01L2221/68345H01L2224/1416H01L2224/16225H01L2224/17106H01L2224/81385H01L2224/81815
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,400,945
App. No.
18/657,689
Granted
Aug 26, 2025
Kind
B2
Abstract

An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

Claims (40)

1. A method for making an electronic device, comprising:

forming a multilevel package substrate having a first level, a second level, a conductive structure, and conductive leads;

forming molded dielectric features and patterning conductive features in the first and second levels;

extending the first level in a plane of a first direction and an orthogonal second direction, the first level including a conductive first trace layer and a conductive first via layer, the first level having a first side with landing areas spaced apart from one another along the first direction;

the second level including a conductive second trace layer and a conductive second via layer, the second trace layer spaced apart from the first trace layer along a third direction that is orthogonal to the first and second directions;

the conductive structure having a first end and a second end that is spaced apart from the first end along the first direction, the conductive structure including conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end;

forming indents in the conductive structure that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction, and the indents positioned along the first direction between respective pairs of the landing areas;

electrically coupling conductive terminals of a die to respective ones of the landing areas; and

enclosing the die and a portion of the multilevel package substrate with a package structure.

2. The method for claim 1 , wherein the indents extend into the conductive features in the second level.

3. The method for claim 2 , wherein the indents extend into the conductive structure along the third direction.

4. The method for claim 3 , wherein the indents extend through the conductive portions in the first level.

5. The method for claim 3 , wherein:

the indents extend through the first trace layer along a third direction; and

the indents laterally surround the landing areas.

6. The method for claim 3 , further including extending second indents into the conductive structure along the second direction.

7. The method for claim 2 , wherein the indents extend into the conductive structure along the second direction.

8. The electronic device of claim 1 , wherein the indents extend into the conductive structure along the third direction.

9. The electronic device of claim 8 , wherein the indents extend through the conductive portions in the first level.

10. The method for claim 8 , wherein:

the indents extend through the first trace layer along a third direction; and

the indents laterally surround the landing areas.

11. The method for claim 1 , wherein the indents extend into the conductive structure along the second direction.

12. A method for making a multilevel package substrate, comprising:

forming a first level;

forming a second level; and

forming a conductive structure;

the first and second levels each having patterned conductive features and molded dielectric features;

the first level extending in a plane of a first direction and an orthogonal second direction, the first level including a conductive first trace layer and a conductive first via layer, the first level having a first side with landing areas spaced apart from one another along the first direction, the landing areas adapted to be soldered to conductive terminals of a die;

the second level including a conductive second trace layer and a conductive second via layer, the second trace layer spaced apart from the first trace layer along a third direction that is orthogonal to the first and second directions;

the conductive structure having a first end and a second end that is spaced apart from the first end along the first direction, the conductive structure including conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end; and

extending indents from the conductive structure into the conductive portions in the first level, the indents spaced apart from one another along the first direction, and the indents positioned along the first direction between respective pairs of the landing areas.

13. The method for claim 12 , wherein the indents extend into the conductive features in the second level.

14. The method for claim 13 , wherein the indents extend into the conductive structure along the second direction.

15. The method for claim 12 , wherein the indents extend into the conductive structure along the third direction.

16. The method for claim 15 , wherein the indents extend through the conductive portions in the first level.

17. The method for claim 15 , wherein:

the indents extend through the first trace layer along a third direction; and

the indents laterally surround the landing areas.

18. The method for multilevel package substrate of claim 12 , wherein the indents extend into the conductive structure along the second direction.

Continuity (2)
Continuation 17406150 · Aug 19, 2021
Related Publication 20240297109A1 · Sep 5, 2024
References Cited (20)
US 7989944B2 · Tuominen · 2011 [cited by examiner]
US 8129226B2 · Johnston · 2012 [cited by examiner]
US 8922005B2 · Hu · 2014 [cited by examiner]
US 9107290B1 · Chen · 2015 [cited by examiner]
US 9257386B2 · Arisaka · 2016 [cited by examiner]
US 9466631B2 · Fallica et al. · 2016 [cited by applicant]
US 10068874B2 · Nelson · 2018 [cited by examiner]
US 10153177B2 · Sorimachi · 2018 [cited by examiner]
US 10262932B2 · Furuichi · 2019 [cited by examiner]
US 10905005B2 · Taneda · 2021 [cited by examiner]
US 11417613B2 · Kim · 2022 [cited by examiner]
US 11978699B2 · Ankamah-Kusi · 2024 [cited by examiner]
US 20100212947A1 · Yamanaka et al. · 2010 [cited by applicant]
US 20160066423A1 · Sakamopto et al. · 2016 [cited by applicant]
US 20200066716A1 · Tang et al. · 2020 [cited by applicant]
US 20200211971A1 · Mizutani · 2020 [cited by applicant]
US 20200411416A1 · Koduri et al. · 2020 [cited by applicant]
US 20210143103A1 · Mrad · 2021 [cited by examiner]
US 20210175195A1 · Chen et al. · 2021 [cited by applicant]
PCT Search Report PCT/US2002/040587 mailed Jan. 19, 2023, 2 pages. [cited by applicant]