III-V semiconductor layers, III-V semiconductor devices and methods of manufacturing thereof
A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.
1. A method of manufacturing a gate-all-around field effect transistor (GAA FET), the method comprising:
forming a shallow-trench-isolation (STI) in a silicon (Si) substrate, the STI surrounding a Si region of the silicon substrate;
recessing the Si region;
after the Si region is recessed, forming a compound semiconductor layer on a surface of the recessed Si region;
forming a Group III-V semiconductor layer on the compound semiconductor layer;
after the Group III-V semiconductor layer is formed, recessing the STI so as to expose a part of the compound semiconductor layer under the Group III-V semiconductor layer;
removing the compound semiconductor layer; and
after the compound semiconductor is removed, forming a gate dielectric layer and a metal gate layer around the Group III-V semiconductor layer.
2. The method of claim 1 , further comprising, after the recessing the STI and before the removing the compound semiconductor layer:
forming a dummy dielectric layer on the Group III-V layer;
forming a dummy polysilicon layer on the dummy dielectric layer;
patterning the dummy polysilicon layer, thereby forming a dummy gate;
forming sidewall spacers on opposing side faces of the dummy gate;
after the sidewall spacers are formed, forming a first interlayer dielectric (ILD) layer; and
removing the dummy gate, thereby forming an opening,
wherein the compound semiconductor is removed through the opening.
3. The method of claim 2 , wherein the Group III-V semiconductor layer is an InAs layer.
4. The method of claim 3 , wherein the compound semiconductor layer is an InP layer.
5. The method of claim 4 , wherein the Si substrate has a (100) plane as a principal surface.
6. The method of claim 5 , wherein the Si region is recessed by etching with tetramethylammonium hydroxide.
7. The method of claim 6 , wherein after the compound semiconductor layer is formed, an upper portion of the compound semiconductor layer has two (111) planes forming a triangular cross section.
8. The method of claim 7 , wherein the Group III-V semiconductor layer has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.
9. The method of claim 8 , wherein:
the first convex-rounded corner surface connects the first and second major surfaces,
the concave-rounded corner surface connects the second and third major surfaces,
the second convex-rounded corner surface connects the third and fourth major surfaces, and
the third convex-rounded corner surface connects the fourth and third major surfaces.
10. The method of claim 8 , wherein the second and third major surfaces are in contact with the two (111) planes of the compound semiconductor layer, before the compound semiconductor layer is removed.
11. The method of claim 8 , wherein:
extended planes of the first and second major surfaces make an acute angle,
extended planes of the second and third major surfaces make an angle of 60° to 150°,
extended planes of the third and fourth major surfaces make an acute angle, and
extended planes of the fourth and first major surfaces make an acute angle.
12. The method of claim 11 , wherein the extended planes of the second and third major surfaces make an angle of 90° to 150°.
13. The method of claim 1 , wherein in the removing the compound semiconductor layer, the compound semiconductor layer is partially removed.
14. The method of claim 1 , wherein the gate dielectric layer is also formed between the metal gate layer and the recessed Si region.
15. The method of claim 1 , wherein a void is formed in the metal gate layer between the III-V semiconductor layer and the recessed Si region.
16. A method of manufacturing a gate-all-around field effect transistor (GAA FET), the method comprising:
forming a shallow-trench-isolation (STI) in a silicon (Si) substrate, the STI surrounding a Si region of the silicon substrate;
recessing the Si region;
after the Si region is recessed, forming a compound semiconductor layer on a surface of the recessed Si region;
after the compound semiconductor layer is formed, planarizing an upper portion of the compound semiconductor layer,
forming a Group III-V semiconductor layer on the planarized compound semiconductor layer;
after the Group III-V semiconductor layer is formed, recessing the STI so as to expose a part of the compound semiconductor layer under the Group III-V semiconductor layer;
removing the compound semiconductor layer; and
forming a gate dielectric layer and a metal gate layer around the Group III-V semiconductor layer.
17. The method of claim 16 , further comprising, after the recessing the STI and before the removing the compound semiconductor layer:
forming a dummy dielectric layer on the Group III-V layer;
forming a dummy polysilicon layer on the dummy dielectric layer;
patterning the dummy polysilicon layer, thereby forming a dummy gate;
forming sidewall spacers on opposing side faces of the dummy gate;
after the sidewall spacers are formed, forming a first interlayer dielectric (ILD) layer; and
removing the dummy gate, thereby forming an opening,
wherein the compound semiconductor is removed through the opening.
18. The method of claim 17 , wherein:
the Group III-V semiconductor layer is an InAs layer, and
the compound semiconductor layer is an InP layer.
19. The method of claim 18 , wherein the Group III-V semiconductor layer has a cross section having a substantially triangular shape with rounded corners.