IP Library › Granted Patent US 10,263,522
Granted Patent B2
US 10,263,522 · App. 15/985,155 · Granted Apr 16, 2019

Semiconductor integrated circuit device and power supply system

Inventors: Daisuke Kondo (Tokyo, JP); Koji Tateno (Tokyo, JP); Yumi Kishita (Tokyo, JP); Tomoaki Uno (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H02M3/158H02M1/08H02M3/1588H03K17/063H01L2224/40245H01L2224/48137H01L2924/00014H02M2001/0009H02M2001/0032H02M2001/0054H03K2217/0036Y02B70/1466Y02B70/16
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Quick Facts
Patent No.
US 10,263,522
App. No.
15/985,155
Granted
Apr 16, 2019
Kind
B2
Abstract

A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET.

Claims (46)

1. A semiconductor integrated circuit device comprising:

a first voltage terminal supplied with a first voltage;

a first MOSFET having:

a drain;

a source;

a first input electrode configured to cause a current path to be formed between the source and the drain; and

a second input electrode located closer to the drain than the first input electrode and aligned beside the current path,

the first input electrode partially overlapping with the drain and insulated from the drain and the second input electrode by an insulating material,

the drain being electrically connected to the first voltage terminal;

a first resistance element electrically connected to the source and a connection node; and

a second resistance element electrically connected to the connection node and a ground terminal, which is supplied with a second voltage lower than the first voltage,

wherein the connection node is electrically connected to the second input electrode.

2. The semiconductor integrated circuit device according to claim 1 ,

wherein the first MOSFET has a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region overlaid on the first semiconductor region, and a first-conductivity-type third semiconductor region overlaid on the second semiconductor region,

the drain of the first MOSFET is composed of the first semiconductor region,

the source of the first MOSFET is composed of the third semiconductor region,

the first input electrode of the first MOSFET is composed of a first-conductivity-type material embedded in the second semiconductor region, and

the second input electrode of the first MOSFET is composed of a second-conductivity-type material embedded in the first semiconductor region.

3. The semiconductor integrated circuit device according to claim 1 , wherein the source is electrically connected to an output terminal for connecting to an external load.

4. The semiconductor integrated circuit device according to claim 1 , wherein the first MOSFET, the first resistance element, the second resistance element and the connection node are sealed in one package.

5. The semiconductor integrated circuit device according to claim 1 , further comprising a drive circuit that outputs a drive signal to the first input electrode.

6. The semiconductor integrated circuit device according to claim 5 , wherein the first MOSFET, the first resistance element, the second resistance element, the connection node, and the drive circuit are sealed in one package.

7. The semiconductor integrated circuit device according to claim 6 ,

wherein the drive circuit is formed in a first semiconductor chip,

the first MOSFET is formed in a second semiconductor chip different from the first semiconductor chip, and

the first and second semiconductor chips are sealed in the one package.

8. A method of driving a semiconductor integrated circuit device comprising:

providing a semiconductor integrated circuit device including:

a first voltage terminal;

a first MOSFET having:

a drain electrically connected to the first voltage terminal;

a source;

a first input electrode configured to cause a current path to be formed between the source and the drain; and

a second input electrode located closer to the drain than the first input electrode and aligned beside the current path,

the first input electrode partially overlapping with the drain and insulated from the drain and the second input electrode by an insulating material;

a first resistance element electrically connected to the source;

a second resistance element electrically connected to a ground terminal; and

a connection node electrically connected to the first resistance element, the second resistance element, and the second input electrode;

supplying a first voltage to the first voltage terminal;

supplying a second voltage to the ground terminal; and

inputting a first input voltage to the first input electrode,

wherein an amplitude of a second input voltage supplied to the second input electrode is smaller than an amplitude of voltage of the source, and

the second input voltage follows the voltage of the source.

9. The method of driving a semiconductor integrated circuit device according to claim 8 , wherein the second input voltage is negative in polarity relative to the voltage of the source.

10. The method of driving a semiconductor integrated circuit device according to claim 8 , wherein, when the first MOSFET in its off-state is switched on, a voltage rising in a same manner as the voltage of source is supplied to the second input electrode.

11. The method of driving a semiconductor integrated circuit device according to claim 8 , wherein, when the first MOSFET in its on-state is switched off, the second input voltage is lower than the voltage of source and is negative in polarity relative to the voltage of source.

Continuity (4)
Continuation 15630854 · Jun 22, 2017
Division 15199978 · Jun 30, 2016
Continuation 14418934
Related Publication 20180269789A1 · Sep 20, 2018
Cited By (1)
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