Semiconductor device and manufacturing method thereof
A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.
1. A semiconductor device, comprising:
a first interlayer dielectric (ILD) layer disposed over a substrate;
a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate;
a second ILD layer disposed over the first ILD layer and the first metal wiring pattern; and
a second metal wiring pattern formed in the second ILD layer and connected to the first metal wiring pattern, wherein:
in a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is at least partially covered by a first two-dimensional material layer,
wherein in the cross section, sides and bottom of the first metal wiring pattern are covered by a second two-dimensional material layer,
wherein the first and second two-dimensional material layers are single layers of two-dimensional material,
the first two-dimensional material layer is disposed only over the first metal wiring pattern,
the first and second metal wiring patterns include Cu, and
the second metal wiring pattern passes through the first two-dimensional material layer and is in direct contact with a Cu surface of the first metal wiring pattern.
2. The semiconductor device of claim 1 , wherein the first two-dimensional material layer includes graphene.
3. The semiconductor device of claim 1 , wherein the first two-dimensional material layer includes transition metal dichalcogenide (TMD).
4. The semiconductor device of claim 3 , wherein the TMD includes one of MoS 2 , WS 2 and NbSe 2 .
5. The semiconductor device of claim 1 , wherein the first two-dimensional material layer includes BN.
6. The semiconductor device of claim 1 , wherein in the cross section, sides and bottom of the first metal wiring pattern are covered by a barrier metal layer made of a conductive material different from the first two-dimensional material layer.
7. The semiconductor device of claim 1 , wherein in the cross section, sides and bottom of the first metal wiring pattern are covered by a second two-dimensional material layer made of a two-dimensional material different from the first two-dimensional material layer.
8. A semiconductor device, comprising:
a first interlayer dielectric (ILD) layer disposed over a substrate;
a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate;
a second ILD layer disposed over the first ILD layer and the first metal wiring pattern; and
a second metal wiring pattern formed in the second ILD layer and connected to the first metal wiring pattern, wherein:
in a cross section along a second direction, which crosses the first direction and is in parallel with the substrate, a top of the second metal wiring pattern is fully covered by a first two-dimensional material layer,
wherein the first two-dimensional material layer covering the top of the second metal wiring pattern only covers the second metal wiring pattern,
the first two-dimensional material layer is a single layer of two-dimensional material,
wherein in the cross section, sides and bottom of the first metal wiring pattern are covered by the first two-dimensional material layer,
the first and second metal wiring patterns include Cu, and
the first two-dimensional material layer is in direct contact with a Cu surface of the second metal wiring pattern,
in the cross section, a part of a top of the first metal wiring pattern is covered by a second two-dimensional material layer, and the second metal wiring pattern passes through the second two-dimensional material layer and is in direct contact with a Cu surface of the first metal wiring pattern, and
the second two-dimensional material layer covering the top of the first metal wiring pattern only covers the first metal wiring pattern.
9. The semiconductor device of claim 8 , wherein the first two-dimensional material layer includes graphene.
10. The semiconductor device of claim 8 , wherein the first two-dimensional material layer includes transition metal dichalcogenide (TMD).
11. The semiconductor device of claim 10 , wherein the TMD includes one of MoS 2 , WS 2 and NbSe 2 .
12. The semiconductor device of claim 8 , wherein the first two-dimensional material layer includes BN.
13. The semiconductor device of claim 8 , wherein a material of the first two-dimensional material layer is same as a material of the second two-dimensional material layer.
14. The semiconductor device of claim 8 , wherein in the cross section, sides of the second metal wiring pattern, and sides and bottom of the first metal wiring pattern are covered by barrier metal layer made of a conductive material different from the first two-dimensional material layer.
15. A method of manufacturing a semiconductor device, comprising:
forming a first interlayer dielectric layer over a substrate;
forming a first recess in the first interlayer dielectric layer;
forming a first two-dimensional material layer over sidewalls of the first recess;
forming a first metal wiring pattern over the first two-dimensional material layer in the first recess;
removing a metal oxide layer on an upper surface of the first metal wiring pattern,
wherein the metal oxide layer is a metal oxide of the first metal wiring pattern;
forming a second two-dimensional material layer on a top of the first metal wiring pattern,
wherein the first and second two-dimensional material layers are single layers of two-dimensional material, and
the two-dimensional material layer disposed on a top of the first metal wiring is disposed only over the first metal wiring pattern;
partially removing the two-dimensional material layer to partially expose the upper surface of the first metal wiring pattern;
forming a second interlayer dielectric layer over the first interlayer dielectric layer and the first metal wiring pattern; and
forming a second metal wiring pattern in the second interlayer dielectric layer connected to the first metal wiring pattern.
16. The semiconductor device of claim 1 , wherein a thickness of the first two-dimensional material layer ranges from about 0.3 nm to about 5 nm.
17. The semiconductor device of claim 8 , wherein a thickness of the first two-dimensional material layer ranges from about 0.3 nm to about 5 nm.
18. The method of claim 15 , wherein a thickness of the two-dimensional material layer ranges from about 0.3 nm to about 5 nm.
19. The method according to claim 15 , wherein the two-dimensional material layer includes graphene or BN.
20. The method according to claim 15 , wherein the two-dimensional material layer includes a transition metal dichalcogenide (TMD).