Semiconductor device and manufacturing method thereof
A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
1. A semiconductor device including a non-volatile memory, wherein:
the non-volatile memory includes:
a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate;
an erase gate line; and
a word line, and
an upper surface of the word line includes a first base portion and a second base portion and a protrusion protruding from the first base portion and the second base portion and disposed between the first base portion and the second base portion,
a highest point of the protrusion measured from the substrate is higher than a height of the first base portion and a height of the second base portion from the substrate, and
the second base portion is located between the protrusion and the control gate.
2. The semiconductor device of claim 1 , wherein the highest point of the protrusion is higher than a height of the erase gate line from the substrate.
3. The semiconductor device of claim 1 , wherein the word line and the erase gate line are formed of polysilicon.
4. The semiconductor device of claim 1 , wherein the protrusion includes sidewall spacers made of an insulating material.
5. The semiconductor device of claim 1 , wherein:
the height of the first base portion is different from the height of the second base portion.
6. The semiconductor device of claim 5 , wherein:
the height of the first base portion is smaller than the height of the second base portion.
7. The semiconductor device of claim 5 , wherein the first base portion includes a sidewall spacer made of an insulating material.
8. The semiconductor device of claim 7 , wherein the protrusion includes sidewall spacers made of the insulating material.
9. The semiconductor device of claim 7 , wherein the sidewall spacers of the protrusion are discontinuous with the sidewall spacer of the first base portion.
10. The semiconductor device of claim 1 , wherein an upper surface of the protrusion inclines downward toward the stacked structure.
11. The semiconductor device of claim 1 , wherein a height the highest point of the protrusion is higher than a height of the control gate from the substrate.
12. A semiconductor device including a non-volatile memory, wherein:
the non-volatile memory includes:
a first stacked structure and a second stacked structure, each comprising a first insulating layer, a floating gate, a second insulating layer and a control gate stacked in this order from a substrate;
an erase gate line disposed between the first stacked structure and the second stacked structure; and
a first word line and a second word line disposed such that the first stacked structure is disposed between the first word line and the erase gate line and the second stacked structure is disposed between the second word line and the erase gate line,
the first word line includes a first protrusion and the second word line includes a second protrusion,
an upper surface of the first word line includes a first base portion and a second base portion and a first protrusion protruding from the first base portion and the second base portion and disposed between the first base portion and the second base portion,
an upper surface of the second word line includes a third base portion and a fourth base portion and a second protrusion protruding from the third base portion and the fourth base portion and disposed between the third base portion and the fourth base portion,
a highest point of the first protrusion measured from the substrate is higher than a height of the first base portion and a height of the second base portion from the substrate,
a highest point of the second protrusion measured from the substrate is higher than a height of the third base portion and a height of the fourth base portion from the substrate,
the second base portion is located between the first protrusion and the control gate, and
the fourth base portion is located between the second protrusion and the control gate.
13. The semiconductor device of claim 12 , wherein the highest point of the first protrusion and the highest point of the second protrusion are higher than a height of the erase gate line from the substrate.
14. The semiconductor device of claim 12 , wherein each of the first and second protrusions includes sidewall spacers made of an insulating material.
15. The semiconductor device of claim 12 , wherein:
the height of the first base portion is different from the height of the second base portion, and
the height of the third base portion is different from the height of the fourth base portion.
16. The semiconductor device of claim 15 , wherein:
the height of the first base portion is smaller than the height of the second base portion, and
the height of the third base portion is smaller than the height of the fourth base portion.
17. The semiconductor device of claim 15 , wherein each of the first and third base portions includes a sidewall spacer made of an insulating material.
18. The semiconductor device of claim 17 , wherein:
each of the first and second protrusions includes sidewall spacers made of the insulating material, and
the sidewall spacers of the first and second protrusions are discontinuous with the sidewall spacers of the first base portion and the third base portion, respectively.
19. The semiconductor device of claim 12 , wherein an upper surface of each of the first and second protrusions inclines downward toward the stacked structure.
20. A semiconductor device including a non-volatile memory and a logic circuit, wherein:
the non-volatile memory includes:
a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate;
an erase gate line; and
a word line,
the logic circuit includes a field effect transistor comprising a gate electrode,
an upper surface of the word line includes a first base portion and a second base portion and a protrusion protruding from the first base portion and the second base portion and disposed between the first base portion and the second base portion,
a highest point of the protrusion measured from the substrate is higher than a height of the first base portion and a height of the second base portion from the substrate,
the second base portion is located between the protrusion and the control gate, and
the word line and the gate electrode are formed of polysilicon.