Air gap adjacent a bottom source/drain region of vertical transistor device
A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.
1. A vertical transistor device, comprising:
a vertically-oriented channel semiconductor structure positioned above a semiconductor substrate, wherein the vertically-oriented channel semiconductor structure comprises opposing lateral sidewalls and opposing end walls;
a first bottom spacer positioned above the semiconductor substrate and adjacent the vertically-oriented channel semiconductor structure, wherein the first bottom spacer extends around less than an entirety of a perimeter of the vertically-oriented channel semiconductor structure;
a gate structure positioned around the vertically-oriented channel semiconductor structure, wherein only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure, wherein the air gap extends around at least a majority of the perimeter of the vertically-oriented channel semiconductor structure and the air gap is a continuous air gap that extends along an entirety of the opposing lateral sidewalls and around one of the opposing end walls of the vertically-oriented channel semiconductor structure; and
a second bottom spacer positioned above the semiconductor substrate, wherein an upper portion of the second bottom spacer contacts a material formed around the vertically-oriented channel semiconductor structure such that the second bottom spacer seals the air gap, wherein the second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.
2. The device of claim 1 , wherein the first bottom spacer is positioned under a gate contact portion of the gate structure adjacent an end surface of the vertically-oriented channel semiconductor structure.
3. The device of claim 1 , wherein the material formed around the vertically-oriented channel semiconductor structure is a protective insulating spacer positioned on at least the gate structure and wherein the second bottom spacer contacts the protective insulating spacer.
4. The device of claim 1 , wherein the material formed around the vertically-oriented channel semiconductor structure comprises one of the gate structure or a material positioned on the gate structure.
5. The device of claim 1 , wherein the second bottom spacer has a vertical thickness that is greater than a vertical thickness of the first bottom spacer.
6. A vertical transistor device, comprising:
a vertically-oriented channel semiconductor structure positioned above a semiconductor substrate;
a first bottom spacer positioned above the semiconductor substrate and adjacent the vertically-oriented channel semiconductor structure, wherein the first bottom spacer extends around less than an entirety of a perimeter of the vertically-oriented channel semiconductor structure;
a gate structure positioned around the vertically-oriented channel semiconductor structure, wherein only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure, wherein the air gap extends around at least a majority of the perimeter of the vertically-oriented channel semiconductor structure and the first bottom spacer is positioned under a gate contact portion of the gate structure adjacent an end surface of the vertically-oriented channel semiconductor structure; and
a second bottom spacer positioned above the semiconductor substrate, wherein an upper portion of the second bottom spacer contacts a material formed around the vertically-oriented channel semiconductor structure such that the second bottom spacer seals the air gap, wherein the second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap and greater than a vertical thickness of the first bottom spacer.
7. The device of claim 6 , wherein the vertically-oriented channel semiconductor structure comprises opposing lateral sidewalls and opposing end walls and wherein the air gap is a continuous air gap that extends along an entirety of the opposing lateral sidewalls and around one of the opposing end walls of the vertically-oriented channel semiconductor structure.
8. The device of claim 6 , wherein the material formed around the vertically-oriented channel semiconductor structure is a protective insulating spacer positioned on at least the gate structure and wherein the second bottom spacer contacts the protective insulating spacer.
9. The device of claim 6 , wherein the material formed around the vertically-oriented channel semiconductor structure comprises one of the gate structure or a material positioned on the gate structure.
10. A vertical transistor device, comprising:
a vertically-oriented channel semiconductor structure positioned above a semiconductor substrate;
a first bottom spacer positioned above the semiconductor substrate and adjacent the vertically-oriented channel semiconductor structure, wherein the first bottom spacer extends around less than an entirety of a perimeter of the vertically-oriented channel semiconductor structure;
a gate structure positioned around the vertically-oriented channel semiconductor structure, wherein only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure, wherein the air gap extends around at least a majority of the perimeter of the vertically-oriented channel semiconductor structure;
a protective insulating spacer positioned on at least the gate structure; and
a second bottom spacer positioned above the semiconductor substrate, wherein an upper portion of the second bottom spacer contacts the protective insulating spacer such that the second bottom spacer seals the air gap, wherein the second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.
11. The device of claim 10 , wherein the first bottom spacer is positioned under a gate contact portion of the gate structure adjacent an end surface of the vertically-oriented channel semiconductor structure.
12. The device of claim 10 , wherein the vertically-oriented channel semiconductor structure comprises opposing lateral sidewalls and opposing end walls and wherein the air gap is a continuous air gap that extends along an entirety of the opposing lateral sidewalls and around one of the opposing end walls of the vertically-oriented channel semiconductor structure.
13. The device of claim 10 , wherein the second bottom spacer has a vertical thickness that is greater than a vertical thickness of the first bottom spacer.