Chip encapsulating method and chip encapsulating structure
A chip encapsulating method includes: fixing a plurality of wafers to a first panel level substrate, the wafer including a plurality of chips; forming a re-distribution layer on the wafer for each of the chips; forming each individual chip and the re-distribution layer connected to the chip by cutting; fixing the chip and the re-distribution layer connected thereto to a second panel level substrate; and encapsulating the chip to form an encapsulating layer. A chip encapsulating structure is prepared by the above described chip encapsulating method.
1. A chip encapsulating method, comprising:
fixing a plurality of wafers to a first panel level substrate, a wafer comprising a plurality of chips;
forming a re-distribution layer on the wafer for each of the chips;
forming each individual chip and the re-distribution layer connected to the chip by cutting;
fixing the chip and the re-distribution layer connected to the chip to a second panel level substrate; and
encapsulating the chip to form an encapsulating layer.
2. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate, the re-distribution layer is close to the second panel level substrate;
after the chip is encapsulated, the chip encapsulating method further comprises:
removing the second panel level substrate;
fixing the encapsulating layer to a third panel level substrate, and forming a solder ball on one side of the re-distribution layer.
3. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate, the re-distribution layer is close to the second panel level substrate;
after the chip is encapsulated, the chip encapsulating method further comprises:
cutting the encapsulating layer, to form each individual chip encapsulating body; and
forming a solder ball for each of the chip encapsulating body.
4. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate, the re-distribution layer is away from the second panel level substrate;
after the chip is encapsulated, the chip encapsulating method further comprises:
decapsulating the encapsulating layer, to expose a contact portion of the re-distribution layer contacting a solder ball; and
forming the solder ball.
5. The chip encapsulating method of claim 1 , wherein after the re-distribution layer is formed and before forming each individual chip and the re-distribution layer connected to the chip by cutting, the method further comprises:
removing the first panel level substrate.
6. The chip encapsulating method of claim 1 , wherein a shape of the wafer is a regular polygon; and
a plurality of the wafers is seamlessly arranged on the first panel level substrate.
7. The chip encapsulating method of claim 6 , wherein the wafer has a rectangular or regular hexagon shape.
8. The chip encapsulating method of claim 1 , wherein the second panel level substrate is a tempered glass substrate.
9. The chip encapsulating method of claim 1 , wherein the first panel level substrate and the second panel level substrate have an identical size.
10. The chip encapsulating method of claim 2 , wherein the first panel level substrate and the second panel level substrate have an identical size.
11. The chip encapsulating method of claim 3 , wherein the first panel level substrate and the second panel level substrate have an identical size.
12. The chip encapsulating method of claim 4 , wherein the first panel level substrate and the second panel level substrate have an identical size.
13. The chip encapsulating method of claim 9 , wherein the third panel level substrate and the first panel level substrate, the second panel level substrate have an identical size when the encapsulating layer is fixed to the third panel level substrate.
14. The chip encapsulating method of claim 10 , wherein the third panel level substrate and the first panel level substrate, the second panel level substrate have an identical size when the encapsulating layer is fixed to the third panel level substrate.
15. The chip encapsulating method of claim 11 , wherein the third panel level substrate and the first panel level substrate, the second panel level substrate have an identical size when the encapsulating layer is fixed to the third panel level substrate.
16. A chip encapsulating structure, comprising:
a plurality of wafers fixed to a first panel level substrate, a wafer comprising a plurality of chips;
a re-distribution layer for each of the chips formed on the wafer;
the plurality of chips being individual chips having the re-distribution layer connected to the chips; and
the chip and the re-distribution layer connected to the chip being fixed to a second panel level substrate; wherein a shape of the wafer is a regular polygon; and a plurality of the wafers are seamlessly arranged on the first panel level substrate.
17. The chip encapsulating structure of claim 16 , wherein the wafer has a rectangular or regular hexagon shape.
18. The chip encapsulating structure of claim 16 , wherein the first panel level substrate and the second panel level substrate have an identical size.