IP Library › Granted Patent US 10,296,033
Granted Patent B2
US 10,296,033 · App. 15/610,674 · Granted May 21, 2019

Substrate voltage control circuit

Inventor: Kazuhiro Adachi (Osaka, JP)
Assignee: PANASONIC CORPORATION
G05F3/205
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Quick Facts
Patent No.
US 10,296,033
App. No.
15/610,674
Granted
May 21, 2019
Kind
B2
Abstract

A substrate voltage control circuit comprising: a first connection terminal; a second connection terminal; a substrate voltage control terminal; a first switch having a first source, a first drain, and a first gate, the first source being connected to the substrate voltage control terminal, the first drain being connected to the first connection terminal; a first resistor connected between the first gate and the second connection terminal; a second switch having a second source, a second drain, and a second gate, the second source being connected to the substrate voltage control terminal, the second drain being connected to the second connection terminal; and a second resistor connected between the second gate and the first connection terminal.

Claims (49)

1. A substrate voltage control circuit comprising:

a first connection terminal;

a second connection terminal;

a substrate voltage control terminal;

a first switch having a first source, a first drain, and a first gate, the first source being connected to the substrate voltage control terminal, the first drain being connected to the first connection terminal;

a first resistor connected between the first gate and the second connection terminal;

a second switch having a second source, a second drain, and a second gate, the second source being connected to the substrate voltage control terminal, the second drain being connected to the second connection terminal; and

a second resistor connected between the second gate and the first connection terminal,

wherein the first switch becomes in an ON state and causes the first source and the first drain to be short-circuited to each other when voltage at the first gate relative to voltage at the first source is higher than threshold voltage of the first switch,

the first switch becomes in an OFF state and causes the first source and the first drain to be open-circuited to each other when the voltage at the first gate relative to the voltage at the first source is lower than the threshold voltage of the first switch,

the second switch becomes in an ON state and causes the second source and the second drain to be short-circuited to each other when voltage at the second gate relative to voltage at the second source is higher than threshold voltage of the second switch, and

the second switch becomes in an OFF state and causes the second source and the second drain to be open-circuited to each other when the voltage at the second gate relative to the voltage at the second source is lower than the threshold voltage of the second switch.

2. The substrate voltage control circuit according to claim 1 , wherein the first resistor and the second resistor each have a resistance value that is greater than or equal to 500Ω and less than or equal to 500 kΩ.

3. The substrate voltage control circuit according to claim 1 , wherein each of the first switch and the second switch is one of a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, a junction field effect transistor, a static induced transistor, and a high electron mobility transistor.

4. The substrate voltage control circuit according to claim 1 , wherein

the first switch includes a first body diode configured such that current flows from the first source to the first drain via the first body diode when voltage at the first source is higher than voltage at the first drain, and

the second switch includes a second body diode configured such that current flows from the second source to the second drain via the second body diode when voltage at the second source is higher than voltage at the second drain.

5. A module comprising:

a bidirectional switch including a first terminal, a second terminal, and a substrate terminal; and

the substrate voltage control circuit according to claim 1 , wherein

the first connection terminal, the second connection terminal, and the substrate voltage control terminal of the substrate voltage control circuit are connected with the first terminal, the second terminal, and the substrate terminal of the bidirectional switch, respectively.

6. The module according to claim 5 , wherein the substrate voltage control circuit causes voltage at the substrate terminal to be equal to the lower one of voltage at the first terminal and voltage at the second terminal.

7. A substrate voltage control circuit comprising:

a first connection terminal;

a second connection terminal;

a substrate voltage control terminal;

a first switch having a first source, a first drain, and a first gate, the first source being connected to the substrate voltage control terminal, the first drain being connected to the first connection terminal;

a first resistor connected between the first gate and the second connection terminal;

a second switch having a second source, a second drain, and a second gate, the second source being connected to the substrate voltage control terminal, the second drain being connected to the second connection terminal;

a second resistor connected between the second gate and the first connection terminal;

a first diode having a first anode and a first cathode, the first anode being connected to the first gate, the first cathode being connected to the second connection terminal; and

a second diode having a second anode and a second cathode, the second anode being connected to the second gate, the second cathode being connected to the first connection terminal,

wherein

the first diode causes voltage at the first gate to be lower than threshold voltage of the first switch so as to set the first switch to an OFF state, by the time that voltage at the second connection terminal becomes equal to voltage at the first connection terminal, and

the second diode causes voltage at the second gate to be lower than threshold voltage of the second switch so as to set the second switch to an OFF state, by the time that the voltage at the first connection terminal becomes equal to the voltage at the second connection terminal.

8. A substrate voltage control circuit comprising:

a first connection terminal;

a second connection terminal;

a substrate voltage control terminal;

a first switch having a first source, a first drain, and a first gate, the first source being connected to the substrate voltage control terminal, the first drain being connected to the first connection terminal;

a first resistor connected between the first gate and the second connection terminal;

a second switch having a second source, a second drain, and a second gate, the second source being connected to the substrate voltage control terminal, the second drain being connected to the second connection terminal;

a second resistor connected between the second gate and the first connection terminal;

a first capacitor connected between the first connection terminal and the first gate; and

a second capacitor connected between the second connection terminal and the second gate.

9. The substrate voltage control circuit according to claim 8 , wherein

the first capacitor suppresses drop of voltage at the first gate such that the first switch keeps in an ON state, until voltage at the second connection terminal relative to voltage at the first connection terminal decreases to be close to 0 V in a positive voltage range, and

the second capacitor suppresses drop of voltage at the second gate such that the second switch keeps in an ON state, until the voltage at the second connection terminal relative to the voltage at the first connection terminal increases to be close to 0 V in a negative voltage range.

10. The substrate voltage control circuit according to claim 8 , wherein the first capacitor and the second capacitor each have a capacitance value that is greater than or equal to 100 pF and less than or equal to 10 nF.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2017
From: ADACHI, KAZUHIRO
To: PANASONIC CORPORATION
Reel/Frame 043162/0140 →
Priority Claims (4)
JP 2016-114282 · Jun 8, 2016 · national
JP 2016-114283 · Jun 8, 2016 · national
JP 2016-114400 · Jun 8, 2016 · national
JP 2017-005222 · Jan 16, 2017 · national
Continuity (1)
Related Publication 20170357283A1 · Dec 14, 2017
Cited By (3)
US 12,356,730 US 12,489,437 US 12,512,664