IP Library › Granted Patent US 10,310,810
Granted Patent B2
US 10,310,810 · App. 15/703,769 · Granted Jun 4, 2019

Memory system and method for controlling nonvolatile memory

Inventor: Naoya Fukuchi (Tokyo, JP)
Assignee: Toshiba Memory Corporation
G06F5/10G06F3/0656G06F3/0659G06F3/0679G06F13/385
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Quick Facts
Patent No.
US 10,310,810
App. No.
15/703,769
Granted
Jun 4, 2019
Kind
B2
Abstract

A memory system including a nonvolatile memory and a controller configured to control the nonvolatile memory, and a method executed by the memory system, wherein the controller fetches a first command in a submission queue on a memory of a host to a first queue in the memory system and executes the first command, checks contents of a subsequent command in the submission queue or another submission queue while leaving the subsequent command in the submission queue or the other submission queue, fetches the subsequent command to a second queue in the memory system, and executes the subsequent command and the first command in parallel, when the subsequent command is a command executable during the execution of the first command.

Claims (32)

1. A memory system connectable a host, the memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein

the controller is further configured to:

fetch a first command in a submission queue on a memory of the host to a first queue in the memory system;

execute the first command;

check contents of a subsequent command in the submission queue or another submission queue on the memory of the host during the execution of the first command while leaving the subsequent command in the submission queue or said another submission queue; and

fetch the subsequent command from the submission queue or said another submission queue to a second queue in the memory system and execute the subsequent command and the first command in parallel, when the subsequent command is a command executable during the execution of the first command.

2. The memory system of claim 1 , wherein the controller is configured to refer to an entry of the submission queue or of said another submission queue pointed by a head pointer corresponding to the submission queue or to said another submission queue without updating the head pointer to check the contents of the subsequent command while leaving the subsequent command in the submission queue or said another submission queue.

3. The memory system of claim 2 , wherein the controller is further configured to fetch the subsequent command and update the head pointer corresponding to the submission queue or the said another submission queue, when the subsequent command is a command executable during the execution of the first command.

4. The memory system of claim 1 , wherein the controller is further configured to not fetch the subsequent command from the submission queue or said another submission queue, when the subsequent command is not a command executable during the execution of the first command.

5. The memory system of claim 1 , wherein the first queue and the second queue exist on a random access memory in the memory system.

6. A memory system connectable to a host, the memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein

the controller is further configured to:

fetch a first command in a first submission queue on a memory of the host to a first queue in the memory system;

execute the first command;

check contents of a first subsequent command in a second submission queue on the memory of the host during the execution of the first command while leaving the first subsequent command in the second submission queue;

fetch the first subsequent command from the second submission queue to a second queue in the memory system and execute the first subsequent command and the first command in parallel, when the first subsequent command is a command which is executable during the execution of the first command;

check contents of a second subsequent command in a third submission queue on the memory of the host while leaving the second subsequent command in the third submission queue, when the first subsequent command is not a command which is executable during the execution of the first command; and

fetch the second subsequent command from the third submission queue to the second queue and execute the second subsequent command and the first command in parallel, when the second subsequent command is a command which is executable during the execution of the first command.

7. The memory system of claim 6 , wherein the controller is further configured to:

refers to an entry in the second submission queue pointed by a head pointer corresponding to the second submission queue without updating the head pointer corresponding to the second submission queue to check the contents of the first subsequent command while leaving the first subsequent command in the second submission queue; and

refer to an entry in the third submission queue pointed by a head pointer corresponding to the third submission queue without updating the head pointer corresponding to the third submission queue to check contents of the second subsequent command while leaving the second subsequent command in the third submission queue, when the first subsequent command is not a command which is executable during the execution of the first command.

8. A method executed by a memory system including a nonvolatile memory and a controller configured to control the nonvolatile memory, the method comprising:

fetching a first command in a submission queue on a memory of a host to a first queue in the memory system;

executing the first command;

checking contents of a subsequent command in the submission queue or another submission queue on the memory of the host during the execution of the first command while leaving the subsequent command in the submission queue or said another submission queue; and

fetching the subsequent command from the submission queue or said another submission queue to a second queue in the memory system and executing the subsequent command and the first command in parallel, when the subsequent command is a command executable during the execution of the first command.

9. The method of claim 8 , wherein the checking of contents of the subsequent command while leaving the subsequent command in the submission queue or in said another submission queue includes referring to an entry in the submission queue or a different submission queue pointed by a head pointer corresponding to the submission queue or said another submission queue without updating the head pointer.

10. The method of claim 9 , wherein when the subsequent command is a command executable during the execution of the first command, the subsequent command is fetched and the head pointer is updated.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: FUKUCHI, NAOYA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 044403/0741 →
Priority Claims (1)
JP 2017-066789 · Mar 30, 2017 · national
Continuity (1)
Related Publication 20180285073A1 · Oct 4, 2018
Cited By (3)
US 12,271,628 US 12,386,555 US 12,481,429