Circuit interrupter including electronic trip unit and method of determining elapsed time of start-up process

1. A circuit interrupter electrically connected to a circuit, the circuit interrupter comprising:

separable contacts structured to open to interrupt current flowing through the circuit interrupter;

an operating mechanism structured to trip open the separable contacts;

a power supply structured to use power flowing through the circuit interrupter to provide power to components of the circuit interrupter; and

an electronic trip unit structured to receive power from the power supply and including:

a processor structured to detect faults in the circuit based on inputs from one or more sensors and to cause the operating mechanism to trip open the separable contacts in response to detecting a fault; and

a timing circuit including a capacitor structured to begin charging when the electronic trip unit begins receiving power from the power supply,

wherein the electronic trip unit includes a start-up process and is structured to proceed through the start-up process when the electronic trip unit begins receiving power from the power supply,

wherein the processor is structured to read a voltage across the capacitor when the start-up process has completed and to determine an elapsed time of the start-up process based on the read voltage across the capacitor, and

wherein the circuit interrupter is associated with one or more trip times, wherein the processor is structured to adjust at least one trip time based on the determined elapsed time of the start-up process, and wherein the processor is structured to use the adjusted trip time to determine when to cause the operating mechanism to trip open the separable contacts.

2. The circuit interrupter of claim 1 , wherein the electronic trip unit further includes:

a secondary power supply structured to convert power from the power supply into a voltage usable by the processor;

a reset circuit structured to hold the processor in a reset state until the voltage is stable.

3. The circuit interrupter of claim 1 , wherein the processor is structured to use the adjusted trip time when the detected fault is detected upon the processor completing the start-up process.

4. The circuit interrupter of claim 1 , wherein the processor is structured to determine a relation between elapsed time and the voltage across the capacitor using a calibration process.

5. The circuit interrupter of claim 4 , wherein, in the calibration process, the processor is structured to cause the capacitor to discharge, to allow the capacitor to charge for a fixed amount of time, and to read the voltage across the capacitor at an end of the fixed amount of time.

6. The circuit interrupter of claim 1 , wherein the timing circuit further includes:

a resistor, wherein the resistor and the capacitor are electrically coupled between a voltage source provided by the power supply and ground.

7. The circuit interrupter of claim 5 , wherein the timing circuit further includes:

a buffer electrically coupled between the capacitor and the processor; and

an analog to digital converter electrically connected between the capacitor and the processor,

wherein the analog to digital converter is structured to convert the voltage across the capacitor to a digital value.

8. The circuit interrupter of claim 6 , wherein the timing circuit further includes:

a discharge switch electrically connected across the capacitor,

wherein closing the discharge switch causes the capacitor to discharge and opening the discharge switch allows the capacitor to charge, and

wherein the processor is structured to control the discharge switch.

9. The circuit interrupter of claim 1 , wherein, in the start-up process, the processor is structured to be released from a reset state.

10. The circuit interrupter of claim 9 , wherein, in the start-up process, the processor is structure to wait for a phase-lock-loop clock to become available or to complete execution of initialization code.

11. A method of determining an elapsed time of a start-up process of an electronic trip unit of a circuit interrupter, the method comprising:

providing a timing circuit including a capacitor structured to begin charging when the electronic trip unit begins to receive power;

performing a start-up process of the electronic trip unit when the electronic trip unit begins to receive power;

reading a voltage across the capacitor when the start-up process has completed;

determining an elapsed time of the start-up process based on the read voltage across the capacitors;

adjusting at least one trip time associated with the circuit interrupter based on the determined elapsed time of the start-up process; and

using the adjusted trip time to determine when to output a trip signal.

12. The method of claim 11 , wherein the adjusted trip time is used when a fault is detected upon completion of the start-up process.

13. The method of claim 11 , further comprising:

determining a relation between elapsed time and the voltage across the capacitor using a calibration process.

14. The method of claim 13 , wherein the calibration process comprises:

causing the capacitor to discharge;

allowing the capacitor to charge for a fixed amount of time; and

reading the voltage across the capacitor at an end of the fixed amount of time.

15. The method of claim 11 , wherein the timing circuit further includes:

a resistor, wherein the resistor and the capacitor are electrically coupled between a voltage source and a ground.

16. The method of claim 15 , wherein the timing circuit further includes:

a buffer electrically coupled to the capacitor; and

an analog to digital converter electrically coupled to the buffer,

wherein the analog to digital converter is structured to convert the voltage across the capacitor to a digital value.

17. The method of claim 15 , wherein the timing circuit further includes:

a discharge switch electrically connected across the capacitor,

wherein closing the discharge switch causes the capacitor to discharge and opening the discharge switch allows the capacitor to charge.

18. The method of claim 11 , wherein the start-up process includes:

releasing an internal clock.

19. The method of claim 18 , wherein the start-up process includes:

waiting for a phase-lock-loop clock to become available or completing execution of initialization code.