Vertical field effect transistor having U-shaped top spacer
A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.
1. A method of forming a semiconductor structure for reducing parasitic capacitance, the method comprising:
forming recesses between a plurality of fins;
depositing a barrier layer within the recesses; and
etching the barrier layer to define substantially U-shaped spacers adjacent top portions of the plurality of fins.
2. The method of claim 1 , further comprising forming a high-k metal gate (HKMG) over the plurality of fins before depositing the barrier layer.
3. The method of claim 2 , further comprising etching the HKMG to form the recesses between the plurality of fins.
4. The method of claim 3 , further comprising forming an epitaxial layer over the plurality of fins.
5. The method of claim 4 , further comprising depositing a nitride cap over the epitaxial layer.
6. The method of claim 5 , wherein air gaps are defined between the U-shaped spacers and the epitaxial layer.
7. The method of claim 6 , wherein an upper surface of the U-shaped spacers contacts the epitaxial layer.
8. The method of claim 6 , wherein the U-shaped spacers contact at least one portion of their corresponding HKMG.
9. The method of claim 6 , wherein the U-shaped spacers are in alignment with at least one portion of their corresponding HKMG.
10. The method of claim 6 , wherein the U-shaped spacers have different sizes across the semiconductor structure.
11. A semiconductor structure for reducing parasitic capacitance, the semiconductor structure comprising:
a plurality of fins including recesses therebetween;
a barrier layer disposed within the recesses; and
U-shaped spacers defined adjacent top portions of the plurality of fins by etching the barrier layer.
12. The structure of claim 11 , wherein a high-k metal gate (HKMG) is disposed over the plurality of fins.
13. The structure of claim 12 , wherein the HKMG is etched to form the recesses between the plurality of fins.
14. The structure of claim 13 , wherein an epitaxial layer is disposed over the plurality of fins.
15. The structure of claim 14 , wherein a nitride cap is disposed over the epitaxial layer.
16. The structure of claim 15 , wherein air gaps are defined between the U-shaped spacers and the epitaxial layer.
17. The structure of claim 16 , wherein an upper surface of the U-shaped spacers contacts the epitaxial layer.
18. The structure of claim 16 , wherein the U-shaped spacers contact at least one portion of their corresponding HKMG.
19. The structure of claim 16 , wherein the U-shaped spacers are in alignment with at least one portion of their corresponding HKMG.
20. The structure of claim 16 , wherein the U-shaped spacers have different sizes across the semiconductor structure.