Variable width memory module supporting enhanced error detection and correction
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
1. A memory module with an anterior module side and a posterior module side, the memory module comprising:
a first memory component on the anterior module side;
a second memory component on the posterior module side;
a data-buffer component having:
a primary data link of a first data width;
a first secondary data link, of a second data width, coupled to the first memory component; and
a second secondary data link, of the second data width, coupled to the second memory component;
the data-buffer component to time-division multiplex data from the first memory component on the first secondary data link and the second memory component on the second secondary data link onto the primary data link.
2. The memory module of claim 1 , wherein the first data width equals the second data width.
3. The memory module of claim 1 , wherein the data-buffer component communicates the data over the primary data link at a first rate and over the first secondary data link at a second rate less than the first rate.
4. The memory module of claim 3 , wherein the data-buffer component communicates the data over the second secondary data link at the second rate.
5. The memory module of claim 1 , further comprising:
a third memory component on the anterior module side; and
a fourth memory component on the posterior module side;
the data-buffer component further having:
a third secondary data link, of the second data width, coupled to the third memory component; and
a fourth secondary data link, of the second data width, coupled to the fourth memory component.
6. The memory module of claim 1 , the data-buffer component further having a second primary data link of the first data width.
7. The memory module of claim 1 , the first memory component including DRAM dies.
8. The memory module of claim 1 , the first memory component including a memory package encompassing at least one DRAM die.
9. A memory system comprising:
a memory-controller component having a primary data port; and
a memory module having an anterior module side and a posterior module side, the memory module comprising:
a first memory component on the anterior module side;
a second memory component on the posterior module side;
a data-buffer component having:
a primary data link of a first data width coupled to the primary data port of the memory-controller component;
a first secondary data link, of a second data width, coupled to the first memory component; and
a second secondary data link, of the second data width, coupled to the second memory component;
the data-buffer component to time-division multiplex data from the first memory component on the first secondary data link and the second memory component on the second secondary data link onto the primary data link.
10. The memory system of claim 9 , the memory-controller component having a second primary data port and the data-buffer component having a second primary data link coupled to the second primary data port.
11. The memory system of claim 10 , further comprising a continuity module, wherein second primary data port is coupled to the second primary data link bypassing the continuity module.
12. The memory system of claim 9 , the memory-controller component having a second primary data port, the memory system further comprising:
a second memory module having an anterior module side and a posterior module side, the second memory module comprising:
a first memory component on the anterior module side;
a second memory component on the posterior module side;
a data-buffer component having:
a primary data link of a first data width coupled to the second primary data port of the memory-controller component;
a first secondary data link, of a second data width, coupled to the first memory component; and
a second secondary data link, of the second data width, coupled to the second memory component;
the data-buffer component to time-division multiplex data from the first memory component on the first secondary data link and the second memory component on the second secondary data link onto the primary data link.
13. The memory system of claim 12 , wherein the first data width equals the second data width.
14. The memory system of claim 12 , wherein the data-buffer component communicates the data over the primary data link at a first rate and over the first secondary data link at a second rate less than the first rate.
15. The memory system of claim 14 , wherein the data-buffer component communicates the data over the second secondary data link at the second rate.
16. The memory system of claim 12 , further comprising:
a third memory component on the anterior module side; and
a fourth memory component on the posterior module side;
the data-buffer component further having:
a third secondary data link, of the second data width, coupled to the third memory component; and
a fourth secondary data link, of the second data width, coupled to the fourth memory component.
17. The memory system of claim 12 , the data-buffer component further having a second primary data link of the first data width.
18. The memory system of claim 12 , the first memory component including DRAM dies.
19. The memory system of claim 12 , the first memory component including a memory package encompassing at least one DRAM die.
20. A memory module with an anterior module side and a posterior module side, the memory module comprising:
a first memory component on the anterior module side;
a second memory component on the posterior module side;
a data-buffer component having:
a primary data link of a first data width;
a first secondary data link, of a second data width, coupled to the first memory component;
a second secondary data link, of the second data width, coupled to the second memory component; and
means for time-division multiplexing data from the first memory component on the first secondary data link and the second memory component on the second secondary data link onto the primary data link.