Variable width memory module supporting enhanced error detection and correction
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
1 . A method of reading from a memory system having first memory components on a first memory module and a second memory components on a second memory module, the method comprising:
receiving a read command, addressed to the first memory module, at the first memory module and the second memory module;
the first memory module, responsive to the read command:
reading first and second data from the first memory components;
sending the first data to a memory controller; and
sending the second data to the second memory module; and
the second memory module, responsive to the read command:
holding the second memory components in a low-power mode; and
forwarding the second data to the memory controller.
2 . The method of claim 1 , wherein the second memory module introduces a module delay in the second data, the method further comprising the first memory module, responsive to the read command, adding the module delay to the first data to align the first data with the second data.
3 . The method of claim 1 , the first memory module, responsive to the read command, interleaving the first data from ones of the first memory components and the second data from others of the first memory components.
4 . The method of claim 3 , wherein the interleaving comprises time-division multiplexing.
5 . The method of claim 1 , further comprising:
receiving a second read command addressed to the second memory at the second memory module and the second memory module;
the second memory module, responsive to the second read command:
reading third and fourth data from the second memory components;
sending the third data to the memory controller; and
sending the fourth data to the first memory module; and
the first memory module, responsive to the second read command:
holding the first memory components in the low-power mode; and
forwarding the fourth data to the memory controller.
6 . The method of claim 5 , wherein the first memory module introduces the module delay in the third data, the method further comprising the second memory module, responsive to the second read command, adding the module delay to the third data.
7 . The method of claim 6 , the first memory module, responsive to the read command, interleaving the third data from ones of the second memory components and the fourth data from others of the second memory components.
8 . A memory system comprising:
a memory controller to issue a read command;
a first memory module coupled to the memory controller to receive the read command, the first memory module having first memory components, a first data buffer coupled to the first memory components; and a first address buffer coupled to the first memory components and the first data buffer; and
a second memory module coupled to the memory controller to receive the read command, the second memory module having second memory components, a second data buffer coupled to the second memory components; and a second address buffer coupled to the second memory components and the second data buffer;
the first address buffer, responsive to the read command, directing the first data buffer to read first and second data from the first memory components, send the first data to the memory controller; and send the second data to the second memory module; and
the second address buffer, responsive to the read command, holding the second memory components in a low-power mode and directing the second data buffer to forward the second data to the memory controller.
9 . The memory system of claim 8 , wherein the second data buffer introduces a module delay in the second data and the first data buffer adds the module delay to the first data to align this first data with the second data.
10 . The memory system of claim 8 , the first data buffer to interleave the first data from ones of the first memory components.
11 . The memory system of claim 10 , wherein the interleaving comprises time-division multiplexing.
12 . The memory system of claim 11 , the memory controller to issue a second read command:
the second address buffer, responsive to the second read command, directing the second data buffer to read third data and fourth data from the second memory components, send the third data to the memory controller, and send the fourth data to the first memory module; and
the first address buffer, responsive to the second read command, holding the first memory components in the low-power mode and directing the first data buffer to forward the fourth data to the memory controller.