Reference voltage circuit with flipped-gate transistor

1. A circuit comprising:

first, second, third, and fourth n-channel metal oxide semiconductor (NMOS) transistors, wherein one of the first, second, third and fourth NMOS transistors is a flipped-gate transistor having a gate terminal including a p-type polysilicon implant, and wherein remaining ones of the first, second, third and fourth NMOS transistors have respective gate terminals with n-type polysilicon implants, wherein respective gate terminals of the second and third NMOS transistors are coupled to one another, wherein the second NMOS transistor is the flipped-gate transistor, and wherein a drain terminal of the second NMOS transistor is coupled to a current source; and

a fifth NMOS transistor, wherein respective gate terminals of the first and fifth NMOS transistors are coupled to one another, wherein the first and fifth NMOS transistors form a current mirror, and wherein the fifth NMOS transistor includes a respective gate terminal with an n-type polysilicon implant;

wherein the circuit is configured to generate a reference voltage equal to a sum of respective gate-source voltages of two of the first, second, third, and fourth NMOS transistors minus respective gate-source voltages of a remaining two of the first, second, third, and fourth NMOS transistors.

2. The circuit as recited in claim 1 , wherein at least one of the first, second, third, and fourth NMOS transistors is tuned to have a respective gate length to provide compensation for first and second order temperature related non-linearities.

3. The circuit as recited in claim 1 , wherein the fourth NMOS transistor is coupled in series between the third NMOS transistor and the fifth NMOS transistor, wherein the reference voltage is output from a node coupled to a source terminal of the fourth NMOS transistor.

4. The circuit as recited in claim 1 , wherein the current source is further coupled to a drain terminal of the third NMOS transistor.

5. The circuit as recited in claim 1 , wherein the first NMOS transistor is diode-coupled.

6. A method comprising:

providing at least one current to a reference voltage circuit, the reference voltage circuit including:

first, second, third, and fourth n-channel metal oxide semiconductor (NMOS) transistors, wherein one of the first, second, third and fourth NMOS transistors is a flipped-gate transistor having a gate terminal including a p-type polysilicon implant, and wherein remaining ones of the first, second, third and fourth NMOS transistors have respective gate terminals with n-type polysilicon implants; and

generating a reference voltage based on a sum of gate-source voltages of the first and third NMOS transistors minus gate-source voltages of the second and fourth NMOS transistors;

wherein the first NMOS transistor is the flipped-gate transistor, and wherein the method further comprises:

providing a first current to a drain terminal of the first NMOS transistor;

providing a second current to a drain terminal of the third NMOS transistor;

drawing a third current from a source terminal of the second NMOS transistor;

drawing a fourth current from a source terminal of the fourth NMOS transistor; and

providing the reference voltage as an output from the reference voltage circuit from the source terminal of the fourth NMOS transistor.

7. An integrated circuit comprising:

a voltage regulator circuit configured to supply a regulated supply voltage to a functional circuit block, wherein the regulated supply voltage is based on a reference voltage; and

a reference voltage circuit coupled to supply the reference voltage to the voltage regulator circuit, wherein the reference voltage circuit includes:

first, second, third and fourth transistors, wherein one of the first, second, third and fourth transistors is an anti-doped transistor having a gate terminal having a polysilicon implant of an opposite polarity and wherein remaining ones of the first, second, third and fourth transistors include respective gate terminals with polysilicon implants of a corresponding polarity;

a first current source coupled to a drain terminal of the first transistor, wherein the first transistor is the anti-doped transistor;

a second current source coupled to a drain terminal of the third transistor;

a third current source coupled to respective source terminals of the second and third transistors; and

a fourth current source coupled to a source terminal of the fourth transistor;

wherein respective gate terminals of the third and fourth transistors are coupled to one another

wherein the reference voltage circuit is configured to generate the reference voltage at a value equal to a sum of respective gate-source voltages of the first and third transistors minus respective gate-source voltages of the second and fourth transistors.

8. The integrated circuit as recited in claim 7 , wherein the first, second, third and fourth transistors are n-channel metal oxide semiconductor (NMOS) transistors.

9. The integrated circuit as recited in claim 7 wherein one or more of the first, second, third, and fourth transistors are tuned to have respective gate lengths to provide compensation for first and second order temperature related non-linearities.

10. The integrated circuit as recited in claim 7 , wherein the reference voltage is output from a node coupled to the source terminal of the fourth transistor.