Voltage reference circuit and method for providing reference voltage
Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of the transistor. A bulk and a source of the flipped-gate transistor are coupled to a ground. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of the transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.
1. A voltage reference circuit, comprising:
a transistor;
a flipped-gate transistor, wherein a gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of the transistor, and a bulk and a source of the flipped-gate transistor are coupled to a ground;
a first current mirror unit configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current;
a second current mirror unit configured to drain a second current from the first transistor in response to the mirroring current; and
an output node coupled to a source of the transistor and the second current mirror unit, and configured to output a reference voltage,
wherein size of the flipped-gate transistor is less than that of the first transistor;
wherein the flipped-gate transistor and the transistor form a diode pair.
2. The voltage reference circuit as claimed in claim 1 , wherein the first current and the second current are currents flowing through different current paths.
3. The voltage reference circuit as claimed in claim 1 , further comprising:
a startup and biasing unit, comprising:
a first resistor coupled to a power supply;
a first N-type transistor coupled between the first resistor and the ground;
a second resistor coupled between a gate of the first N-type transistor and the ground; and
a second N-type transistor coupled between the second resistor and the first current mirror unit, having a gate coupled to the first resistor,
wherein the bias current is a current flowing through the second resistor and the second N-type transistor.
4. The voltage reference circuit claimed in claim 1 , wherein the first current mirror unit comprises:
a first P-type transistor coupled to the power supply, wherein a gate and a drain of the first P-type transistor are coupled to a startup and biasing unit;
a second P-type transistor coupled between the power supply and the second current mirror unit, having a gate coupled to the gate and the drain of the first P-type transistor;
a third P-type transistor coupled between the power and the drain of the flipped-gate transistor, having a gate coupled to the gate of the first P-type transistor; and
a fourth P-type transistor coupled between the power and the drain of the transistor, having a gate coupled to the gate of the first P-type transistor,
wherein the bias current is a current flowing through the first P-type transistor, and the mirroring current is a current flowing through the second P-type transistor.
5. The voltage reference circuit as claimed in claim 1 , wherein the second current mirror unit comprises:
a third N-type transistor coupled between the ground and the first current mirror unit; and
a fourth N-type transistor coupled between the ground and the output node, having a gate coupled to a gate and a drain of the third N-type transistor,
wherein the mirroring current is a current flowing through the third N-type transistor.
6. The voltage reference circuit as claimed in claim 1 , wherein a bulk of the transistor is coupled to the output node.
7. The voltage reference circuit as claimed in claim 1 , wherein a current ratio of the first current and the second current is equal to a first value such that the reference voltage has a temperature coefficient of zero.
8. A voltage reference circuit, comprising:
a first diode-connected transistor, wherein a bulk and a source of the first diode-connected transistor are coupled to a ground;
a second diode-connected transistor, wherein gates and drains of the first and second diode-connected transistors are coupled together; and
an output node coupled to a source and a bulk of the second diode-connected transistor, and configured to output a reference voltage,
wherein size of the first diode-connected transistor is less than that of the second diode-connected transistor,
wherein the flipped-gate transistor and the transistor form a diode pair.
9. The voltage reference circuit as claimed in claim 8 , further comprising:
a first current unit configured to provide a first current to the first diode-connected transistor; and
a second current unit configured to provide a second current to the second diode-connected transistor.
10. The voltage reference circuit as claimed in claim 9 , wherein a current ratio of the first current and the second current is equal to a first value such that the reference voltage has a zero temperature coefficient.
11. The voltage reference circuit as claimed in claim 8 , wherein the first diode-connected transistor and the second diode-connected transistor are arranged in independent current paths.
12. The voltage reference circuit as claimed in claim 8 , further comprising:
a first current mirror unit configured to provide a first current to the first diode-connected transistor and a mirroring current in response to a bias current; and
a second current mirror unit configured to provide a second current to the second diode-connected transistor in response to the mirroring current.
13. The voltage reference circuit as claimed in claim 12 , further comprising:
a startup and biasing unit, comprising:
a first resistor coupled to a power supply;
a first N-type transistor coupled between the first resistor and the ground;
a second resistor coupled between a gate of the first N-type transistor and the ground; and
a second N-type transistor coupled between the second resistor and the first current mirror unit, having a gate coupled to the first resistor,
wherein the bias current is a current flowing through the second resistor and the second N-type transistor.
14. The voltage reference circuit claimed in claim 12 , wherein the first current mirror unit comprises:
a first P-type transistor coupled to a power supply, wherein a gate and a drain of the first P-type transistor are coupled to a startup and biasing unit;
a second P-type transistor coupled between the power supply and the second current mirror unit, having a gate coupled to the gate and drain of the first P-type transistor;
a third P-type transistor coupled between the power supply and a drain of the first diode-connected transistor, having a gate coupled to the gate of the first P-type transistor; and
a fourth P-type transistor coupled between the power supply and a drain of the second diode-connected transistor, having a gate coupled to the gate of the first P-type transistor,
wherein the bias current is a current flowing through the first P-type transistor, and the mirroring current is a current flowing through the second P-type transistor.
15. The voltage reference circuit as claimed in claim 12 , wherein the second current mirror unit comprises:
a third N-type transistor coupled between the ground and the first current mirror unit; and
a fourth N-type transistor coupled between the ground and the output node, having a gate coupled to a gate and a drain of the third N-type transistor,
wherein the mirroring current is a current flowing through the third N-type transistor.
16. A method for providing a reference voltage, comprising:
obtaining a first current ratio of a first current of a first flipped-gate transistor to a second current of a first non-flipped-gate transistor in a first circuit, wherein the first current ratio corresponds a temperature coefficient of zero, and the first flipped-gate transistor and the first non-flipped-gate transistor are the same size;
mirroring a bias current to generate a third current across a second flipped-gate transistor and to generate a mirroring current in a second circuit;
mirroring the mirroring current to generate a fourth current across a second non-flipped-gate transistor in the second circuit; and
outputting the reference voltage in response to the fourth current,
wherein a second current ratio of the third current to the fourth current is equal to the first current ratio,
wherein the flipped-gate transistor and the transistor form a diode pair.
17. The method as claimed in claim 16 , wherein the first circuit comprises:
a first current source configured to provide the first current to the first flipped-gate transistor;
the first flipped-gate transistor having a drain and a gate coupled to the first current source;
the first non-flipped-gate transistor having a gate coupled to the gate of the first flipped-gate transistor; and
a second current source configured to drain the second current from the first flipped-gate transistor.
18. The method as claimed in claim 16 , wherein the second circuit comprises:
a startup and bias unit configured to generate the bias current.
19. The method as claimed in claim 16 , wherein the second circuit comprises:
a first current mirror unit configured to provide the third current to the second flipped-gate transistor and the mirroring current in response to the bias current; and
a second current mirror unit configured to drain the fourth current from the second non-flipped-gate transistor in response to the mirroring current,
wherein the second flipped-gate transistor and the second non-flipped-gate transistor are diode-connected, gates of the second flipped-gate transistor and the second non-flipped-gate transistor are coupled together, a bulk and a source of the second flipped-gate transistor are coupled to a ground, and a source and a bulk of the second diode-connected transistor are coupled to the second current mirror unit.
20. The method as claimed in claim 16 , wherein the second flipped-gate transistor and the second non-flipped-gate transistor are arranged in independent current paths of the second circuit.