Granted Patent B2

US 12,656,803 · App. 18/756,323 · Granted Jun 16, 2026

Inventors: Mohammad Al-Shyoukh (Hsinchu, TW); Alex Kalnitsky (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

G05F3/20G05F3/26G05F3/262

Abstract

Claims (74)

1 . A voltage reference comprising:

an operating voltage node;

an input node;

an output node;

a first PMOS transistor comprising a gate and a drain terminal, each coupled to the input node, and a source terminal coupled to the operating voltage node through a first resistor;

second through fourth PMOS transistors, each comprising a gate coupled to the input node and a source terminal coupled to the operating voltage node through a respective one of second through fourth resistors;

an n-type flipped gate transistor comprising a gate and a drain terminal, each coupled to a drain terminal of the second PMOS transistor, and a source terminal coupled to a negative supply voltage node;

a first NMOS transistor comprising a gate coupled to the gate of the n-type flipped gate transistor, a drain terminal coupled to a drain terminal of the third PMOS transistor, and a source terminal connected to the output node;

a second NMOS transistor comprising a gate coupled to a drain terminal of the fourth PMOS transistor, a drain terminal connected to the output node, and a source terminal coupled to the negative supply voltage node through a fifth resistor; and

a third NMOS transistor comprising a drain terminal connected to the output node, and a gate and a source terminal, each coupled to the negative supply voltage node.

2 . The voltage reference of claim 1 , further comprising:

a fourth NMOS transistor comprising a gate and a drain terminal, each coupled to the gate of the second NMOS transistor, and a source terminal coupled to the negative supply voltage node through a sixth resistor.

3 . The voltage reference of claim 1 , further comprising:

a fourth NMOS transistor comprising a gate coupled to the operating voltage node through a sixth resistor, a drain terminal coupled to the input node, and a source terminal coupled to the negative supply voltage node through a seventh resistor; and

a fifth NMOS transistor comprising a gate coupled to the source terminal of the fourth NMOS transistor, a drain terminal coupled to the gate of the fourth NMOS transistor, and a source terminal coupled to the negative supply voltage node.

4 . The voltage reference of claim 1 , wherein the input node is coupled to an external current source.

5 . The voltage reference of claim 1 , wherein

a bulk of the n-type flipped gate transistor is coupled to the negative supply voltage node, and

a bulk of the third NMOS transistor is coupled to the negative supply voltage node.

6 . The voltage reference of claim 1 , wherein a gate electrode of the gate of the n-type flipped gate transistor comprises:

a body region comprising p-type dopants; and

edges comprising n-type dopants.

7 . The voltage reference of claim 1 , wherein

each of the first through fifth resistors comprises a series of one or more unit resistors, and

each unit resistor comprises a serpentine structure having a resistance of one megaohm or greater.

8 . A voltage reference comprising:

an operating voltage node;

an input node;

an output node;

a first PMOS transistor comprising a gate and a drain terminal, each coupled to the input node, and a source terminal coupled to the operating voltage node through a first resistor;

second through fourth PMOS transistors, each comprising a gate coupled to the input node and a source terminal coupled to the operating voltage node through a respective one of second through fourth resistors;

an n-type flipped gate transistor comprising a gate and a drain terminal, each coupled to a drain terminal of the second PMOS transistor, and a source terminal coupled to a negative supply voltage node;

a first NMOS transistor comprising a gate coupled to the gate of the n-type flipped gate transistor, a drain terminal coupled to a drain terminal of the third PMOS transistor, and a source terminal connected to the output node;

a second NMOS transistor comprising a gate coupled to a drain terminal of the fourth PMOS transistor, a drain terminal connected to the output node, and a source terminal coupled to the negative supply voltage node through a fifth resistor;

a third NMOS transistor comprising a drain terminal connected to the output node, and a gate and a source terminal, each coupled to the negative supply voltage node;

a fifth PMOS transistor comprising a source terminal coupled to the drain terminals of the third PMOS transistor and first NMOS transistor, and a drain terminal coupled to the negative supply voltage node; and

a fourth NMOS transistor comprising a gate coupled to the gates of the n-type flipped gate transistor and first NMOS transistor, a drain terminal coupled to the operating voltage node, and a source terminal coupled to a gate of the fifth PMOS transistor.

9 . The voltage reference of claim 8 , further comprising:

a fifth NMOS transistor comprising a gate and a drain terminal, each coupled to the gate of the second NMOS transistor, and a source terminal coupled to the negative supply voltage node through a sixth resistor; and

a sixth NMOS transistor comprising a gate coupled to the gate of the second NMOS transistor, a drain terminal coupled to the gate of the fifth PMOS transistor, and a source terminal coupled to the negative supply voltage node through a seventh resistor.

10 . The voltage reference of claim 9 , wherein

the first through fifth PMOS transistors, the first through sixth NMOS transistors, and the first through seventh resistors are configured to generate a voltage level at the source terminal of the fifth PMOS transistor approximately equal to twice a voltage level at the output node.

11 . The voltage reference of claim 9 , wherein

each of the first through seventh resistors comprises a series of one or more unit resistors, and

each unit resistor comprises a serpentine structure having a resistance of one megaohm or greater.

12 . The voltage reference of claim 8 , further comprising:

a fifth NMOS transistor comprising a gate coupled to the operating voltage node through a sixth resistor, a drain terminal coupled to the input node, and a source terminal coupled to the negative supply voltage node through a seventh resistor; and

a sixth NMOS transistor comprising a gate coupled to the source terminal of the fifth NMOS transistor, a drain terminal coupled to the gate of the fifth NMOS transistor, and a source terminal coupled to the negative supply voltage node.

13 . The voltage reference of claim 8 , wherein the input node is coupled to an external current source.

14 . The voltage reference of claim 8 , wherein

a bulk of the n-type flipped gate transistor is coupled to the negative supply voltage node,

a bulk of the first NMOS transistor is coupled to the output node, and

a bulk of the third NMOS transistor is coupled to the negative supply voltage node.

15 . A method of operating a voltage reference, the method comprising:

receiving an operating voltage at an operating voltage node;

using a gate and a drain terminal of a first PMOS transistor to couple an input node to the operating voltage node through a source terminal of the first PMOS transistor and a first resistor;

using the input node to control second through fourth PMOS transistors, each comprising a gate coupled to the input node and a source terminal coupled to the operating voltage node through a respective one of second through fourth resistors;

using a gate and a drain terminal of an n-type flipped gate transistor to couple a drain terminal of the second PMOS transistor to a negative supply voltage node;

using a first NMOS transistor comprising a gate coupled to the gate of the n-type flipped gate transistor to couple a drain terminal of the third PMOS transistor to an output node through the drain terminal of the first NMOS transistor coupled to the drain terminal of the third PMOS transistor and a source terminal of the first NMOS transistor connected to the output node;

using a gate of a second NMOS transistor coupled to a drain terminal of the fourth PMOS transistor to couple the output node to the negative supply voltage node through a drain terminal of the second NMOS transistor connected to the output node and a source terminal coupled to the negative supply voltage node through a fifth resistor; and

using a gate and a source terminal of a third NMOS transistor to couple the negative supply voltage node to the output node through a drain terminal of the third NMOS transistor connected to the output node.

16 . The method of claim 15 , further comprising:

using a fifth PMOS transistor to couple the drain terminals of the third PMOS transistor and first NMOS transistor to the negative supply voltage node through a source terminal of the fifth PMOS transistor coupled to the drain terminals of the third PMOS transistor and first NMOS transistor and a drain terminal of the fifth NMOS transistor coupled to the negative supply voltage node; and

using a fourth NMOS transistor to control the fifth PMOS transistor by a gate of the fourth NMOS transistor coupled to the gates of the n-type flipped gate transistor and first NMOS transistor, a drain terminal of the fourth NMOS transistor coupled to the operating voltage node, and a source terminal of the fourth NMOS transistor coupled to a gate of the fifth PMOS transistor.

17 . The method of claim 16 , further comprising:

using a gate and a drain terminal of a fifth NMOS transistor to couple the gate of the second NMOS transistor to the negative supply voltage node through a source terminal of the fifth NMOS transistor and a sixth resistor; and

using a sixth NMOS transistor to couple the gate of the fifth PMOS transistor to the negative supply voltage node by a gate of the sixth NMOS transistor coupled to the gate of the second NMOS transistor, a drain terminal of the sixth NMOS transistor coupled to the gate of the fifth PMOS transistor, and a source terminal of the sixth NMOS transistor coupled to the negative supply voltage node through a seventh resistor.

18 . The method of claim 17 , wherein

the using each of the first through fifth PMOS transistors and the first through sixth NMOS transistors comprises generating a voltage level at the source terminal of the fifth PMOS transistor approximately equal to twice a voltage level at the output node.

19 . The method of claim 15 , further comprising:

using a fourth NMOS transistor to couple the input node to the negative supply voltage node by a gate of the fourth NMOS transistor coupled to the operating voltage node through a sixth resistor, a drain terminal of the fourth NMOS transistor coupled to the input node, and a source terminal of the fourth NMOS transistor coupled to the negative supply voltage node through a seventh resistor; and

using a fifth NMOS transistor to couple the gate of the fourth NMOS transistor to the negative supply voltage node by a gate of the fifth NMOS transistor coupled to the source terminal of the fourth NMOS transistor, a drain terminal of the fifth NMOS transistor coupled to the gate of the fourth NMOS transistor, and a source terminal of the fifth NMOS transistor coupled to the negative supply voltage node.

20 . The method of claim 15 , further comprising:

receiving a current at the input node from an external current source.

Assignments (1)

Continuity (5)

References Cited (31)