Memory device and memory controller
According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.
1. A memory controller comprising:
a processor; and
a memory interface, wherein
the processor causes the memory interface to
transmit a first instruction to a memory device, the memory device comprising cell transistors coupled in series, word lines respectively coupled to respective gates of the cell transistors, a first data latch, and a second latch, the first instruction instructing application of a positive voltage to one of the word lines, and
transmit a second instruction after the transmission of the first instruction and before transmitting a third instruction, the third instruction instructing output of data from the memory device, the second instruction being different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch,
the memory device comprising a block including the cell transistors, and
the processor further causes the memory interface to transmit the first instruction in response to the count of reads of data from cell transistors in the block or the count of erasures of data in cell transistors in the block exceeding a reference.
2. The controller according to claim 1 , wherein the first instruction instructs reading data from one of the cell transistors.
3. The controller according to claim 1 , wherein:
one of the cell transistors coupled to the word line stores data of bits, and
the first instruction instructs reading data from the cell transistor without specifying one of the bits.
4. The controller according to claim 1 , wherein the processor further causes the memory interface to transmit the first instruction to the memory device every time a first period lapses.
5. The controller according to claim 1 , wherein the processor further causes the memory interface to transmit the first instruction to the memory device when a detected temperature exceeds a reference.
6. The controller according to claim 1 , wherein the processor further causes the memory interface to instruct reading data in the memory device following the transmission of the first instruction.
7. A memory controller comprising:
a processor; and
a memory interface, wherein
the processor causes the memory interface to
transmit a first instruction to a memory device, the memory device comprising cell transistors coupled in series, word lines respectively coupled to respective gates of the cell transistors, a first data latch, and a second latch, the first instruction instructing application of a positive voltage to one of the word lines,
transmit a second instruction after the transmission of the first instruction and before transmitting a third instruction, the third instruction instructing output of data from the memory device, the second instruction being different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch, and
transmit the first instruction to the memory device when a first temperature detected after detection of a second temperature has a larger difference from the second temperature than a reference.
8. The controller according to claim 7 , wherein the first instruction instructs reading data from one of the cell transistors.
9. The controller according to claim 7 , wherein:
one of the cell transistors coupled to a word line stores data of bits, and
the first instruction instructs reading data from the cell transistor without specifying one of the bits.
10. The controller according to claim 7 , wherein the processor further causes the memory interface to transmit the first instruction to the memory device every time a first period lapses.
11. The controller according to claim 7 , wherein the processor further causes the memory interface to transmit the first instruction to the memory device when a detected temperature exceeds a reference.
12. The controller according to claim 7 , wherein the processor further causes the memory interface to instruct reading data in the memory device following the transmission of the first instruction.
13. A memory controller comprising:
a processor; and
a memory interface, wherein
the processor causes the memory interface to
transmit a first instruction to a memory device, the memory device comprising cell transistors coupled in series, word lines respectively coupled to respective gates of the cell transistors, a first data latch, and a second latch, the first instruction instructing application of a positive voltage to one of the word lines;
transmit a second instruction after the transmission of the first instruction and before transmitting a third instruction, the third instruction instructing output of data from the memory device, the second instruction being different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch; and
instruct reading data in the memory device before without transmitting the third instruction after the transmission of the first instruction.
14. The controller according to claim 13 , wherein the first instruction instructs reading data from one of the cell transistors.
15. The controller according to claim 13 , wherein:
one of the cell transistors coupled to a word line stores data of bits, and
the first instruction instructs reading data from the cell transistor without specifying one of the bits.
16. The controller according to claim 13 , wherein the processor further causes the memory interface to transmit the first instruction to the memory device every time a first period lapses.
17. The controller according to claim 13 , wherein the processor further causes the memory interface to transmit the first instruction to the memory device when a detected temperature exceeds a reference.
18. The controller according to claim 13 , wherein the processor further causes the memory interface to instruct reading data in the memory device following the transmission of the first instruction.
19. The controller according to claim 13 , wherein:
the first instruction instructs reading data from one of the cell transistors,
one of the cell transistors coupled to a word line stores data of bits,
the first instruction instructs reading data from the cell transistor without specifying one of the bits,
the processor further causes the memory interface to transmit the first instruction to the memory device every time a first period lapses,
the memory device comprising a block including the cell transistors,
the processor further causes the memory interface to transmit the first instruction when the count of reads of data from cell transistors in the block or the count of erasures of data in cell transistors in the block exceeds a reference,
the processor further causes the memory interface to transmit the first instruction to the memory device when a detected temperature exceeds a reference,
the processor further causes the memory interface to transmit the first instruction to the memory device when a first temperature detected after detection of a second temperature has a larger difference from the second temperature than a reference, and
the processor further causes the memory interface to instruct reading data in the memory device following the transmission of the first instruction.