Semiconductor device using buffer memory
According to one embodiment, in a semiconductor device, a first chip is electrically connected to a terminal to which a signal from a host is input. The first chip is electrically connected to a second chip and to a third chip in parallel with the second chip. The first chip includes a first buffer memory and a second buffer memory. The first buffer memory corresponds to the second chip. The second buffer memory corresponds to the third chip. The second chip includes a third buffer memory. The third chip includes a fourth buffer memory. A capacity of the first buffer memory is equal to or larger than a capacity of the third buffer memory. A capacity of the second buffer memory is equal to or larger than a capacity of the fourth buffer memory.
1 . A semiconductor device comprising:
a first chip electrically connected to a terminal to which a signal from a host is input, the first chip including a first buffer memory and a second buffer memory;
a second chip to which the first chip is electrically connected, the second chip including a plurality of memory cells; and
a third chip to which the first chip is electrically connected in parallel with the second chip, the third chip including a plurality of memory cells;
wherein the first chip is configured to:
receive a first request from the host,
issue a first command to the second chip after receiving the first request,
receive a second request from the host after receiving the first request, and
issue a second command to the third chip after receiving the second request,
the second chip is configured to:
read first data after receiving the first command and
transmit the read first data to the first chip, and
the third chip is configured to:
read second data after receiving the second command; and
transmit the read second data to the first chip, and wherein
the first chip is configured to perform a first operation of storing the first data received from the second chip into the first buffer memory, a second operation of storing the second data received from the third chip into the second buffer memory, and in parallel with the first operation, a third operation of transmitting and receiving a signal relating to outputting the first data from the first buffer memory to and from the host.
2 . The semiconductor device according to claim 1 , wherein
the first chip is configured to perform, in parallel with the first operation, a fourth operation of transmitting and receiving a signal relating to the first data to and from the second chip.
3 . The semiconductor device according to claim 1 , wherein
the first chip is configured to perform, in parallel with the second operation, a fourth operation of transmitting and receiving a signal relating to outputting the second data from the second buffer memory to and from the host.
4 . The semiconductor device according to claim 1 , wherein
the first chip is configured to perform, in parallel with the second operation, a fourth operation of transmitting and receiving a signal relating to the second data to and from the third chip.
5 . The semiconductor device according to claim 1 , wherein
the first chip is configured to supply a first signal to the second chip based on the issuance of the first command, and
the second chip is configured to read the first data based on the first command and the first signal and transmit the read first data to the first chip.
6 . The semiconductor device according to claim 1 , further comprising:
a first channel that electrically connects the first chip and the second chip; and
a second channel that electrically connects the first chip and the third chip.
7 . The semiconductor device according to claim 6 , wherein
the first chip is configured to control the first channel independently of the host in response to a request for the second chip received from the host, and
the first chip is configured to control the second channel independently of the host in response to a request for the third chip received from the host.
8 . The semiconductor device according to claim 7 , wherein
the request for the second chip is a data output request with respect to the second chip, and
the request for the third chip is a data output request with respect to the third chip.
9 . The semiconductor device according to claim 1 , wherein
each of the second chip and the third chip includes a NAND-type flash memory chip.
10 . The semiconductor device according to claim 1 , wherein
the first chip, the second chip and the third chip are sealed with a mold resin.
11 . A storage system comprising:
the semiconductor device according to claim 1 ;
a host; and
a communication path that is connected to the semiconductor device and the host.
12 . The storage system according to claim 11 , wherein
in the semiconductor device, the first chip is configured to perform, in parallel with the first operation, a fourth operation of transmitting and receiving a signal relating to the first data to and from the second chip.
13 . The storage system according to claim 11 , wherein
in the semiconductor device, the first chip is configured to perform, in parallel with the second operation, a fourth operation of transmitting and receiving a signal relating to outputting the second data from the second buffer memory to and from the host.
14 . The storage system according to claim 11 , wherein
in the semiconductor device, the first chip is configured to perform, in parallel with the second operation, a fourth operation of transmitting and receiving a signal relating to the second data to and from the third chip.
15 . The storage system according to claim 11 , wherein
in the semiconductor device, the first chip is configured to supply a first signal to the second chip based on the issuance of the first command, and
the second chip is configured to read the first data based on the first command and the first signal and transmit the read first data to the first chip.
16 . The storage system according to claim 11 , wherein
the semiconductor device further comprises:
a first channel that electrically connects the first chip and the second chip; and
a second channel that electrically connects the first chip and the third chip.
17 . The storage system according to claim 16 , wherein
in the semiconductor device, the first chip is configured to control the first channel independently of the host in response to a request for the second chip received from the host, and
the first chip is configured to control the second channel independently of the host in response to a request for the third chip received from the host.
18 . The storage system according to claim 17 , wherein
in the semiconductor device, the request for the second chip is a data output request with respect to the second chip, and
the request for the third chip is a data output request with respect to the third chip.
19 . The storage system according to claim 11 , wherein
in the semiconductor device, each of the second chip and the third chip includes a NAND-type flash memory chip.
20 . The storage system according to claim 11 , wherein
in the semiconductor device, the first chip, the second chip and the third chip are sealed with a mold resin.