Enhanced patterning of integrated circuit layer by tilted ion implantation
View Patent ↗Methods for achieving sub-lithographic feature sizes in an integrated circuit (IC) layer are provided that use ion implantation to enhance or reduce the etch rate of a thin masking layer. The etch rates also can be enhanced or reduced at specific locations through multiple implantation steps. The implantation can be performed at tilted angles to achieve sub-lithographic implanted regions that are self-aligned to pre-existing photoresist or hard-mask features over the masking layer on the surface of a substrate. A higher density of features can be achieved in an IC layer than are present in an overlying masking layer with the use of ion implantation.
1. A method of achieving sub-lithographic feature sizes in an integrated circuit (IC) layer comprising:
(a) forming an oxide layer on an integrated circuit (IC) layer to be patterned;
(b) coating a hard masking layer on the oxide layer;
(c) implanting ions into the hard masking layer overlying the oxide layer with ion implantation;
(d) etching the hard masking layer with implanted regions to remove regions of the masking layer and form a patterned hard masking layer with sections of exposed oxide layer;
(e) performing ion implantation to selected sections of the exposed oxide layer through the pattern of the hard masking layer;
(f) removing the sections of exposed oxide layer; and
(g) using the patterned hard masking layer and oxide layer as a mask to pattern the integrated circuit layer.
2. The method of claim 1 , wherein said hard masking layer is a material selected from the group of materials consisting of amorphous silicon (a-Si), amorphous carbon (a-C), silicon-carbon-oxide, polycrystalline silicon, silicon nitride (SiNx or Si 3 N 4 ), silicon oxynitride (SiOxNy), and silicon dioxide (SiO 2 ).
3. The method of claim 1 , wherein the ion implantation comprises:
performing ion implantation at positive tilt angle; and
performing ion implantation at negative tilt angle to selectively damage regions of the hard masking layer, wherein regions between photoresist features remain undamaged due to shadowing effects.
4. The method of claim 1 :
wherein the ions used for ion implantation of the hard masking layer are ions of argon (Ar + ); and
wherein regions of the hard masking layer that are implanted with ions are etched away at an increased rate than non-implanted regions.
5. The method of claim 1 :
wherein the ions used for ion implantation of the hard masking layer are ions selected from the group of ions consisting of oxygen and nitrogen; and
wherein regions of the hard masking layer that are implanted with ions are etched away at a reduced rate than non-implanted regions.
6. The method of claim 1 , further comprising:
applying a photoresist layer on the hard masking layer;
printing features in the photoresist layer exposing sections of the hard masking layer with photolithography to produce a patterned photoresist layer;
implanting ions into portions of the hard masking layer not blocked by the patterned photoresist layer; and
etching away implanted portions of the hard mask layer.
7. The method of claim 1 , further comprising coupling the integrated circuit layer to a base substrate.
8. A method for patterning a semiconductor layer, the method comprising:
(a) forming an oxide layer on a semiconductor layer to be patterned;
(b) coating a hard masking layer on the oxide layer;
(d) etching the hard masking layer to produce a patterned hard masking layer with sections of exposed oxide layer;
(e) performing ion implantation to selected sections of the exposed oxide layer through the pattern of the patterned hard masking layer;
(f) removing the sections of exposed implanted oxide layer; and
(g) patterning the semiconductor layer with the pattern of the oxide layer; and
(i) wherein implanted regions of the oxide layer etch at a different rate than non-implanted regions of the oxide layer.
9. The method of claim 8 , further comprising coupling the semiconductor layer to a base substrate.
10. The method of claim 8 :
wherein the ions used for ion implantation of the oxide layer are ions of argon (Ar + ); and
wherein regions of the oxide layer that are implanted with ions are etched away at an increased rate than non-implanted regions.
11. The method of claim 8 :
wherein the ions used for ion implantation of the oxide layer are ions selected from the group of ions consisting of oxygen and nitrogen; and
wherein regions of the oxide layer that are implanted with ions are etched away at a reduced rate than non-implanted regions.
12. The method of claim 8 , wherein said hard masking layer is a material selected from the group of materials consisting of amorphous silicon (a-Si), amorphous carbon (a-C), silicon-carbon-oxide, SiO 2 , polycrystalline silicon and d silicon nitride (SiNx or Si 3 N 4 ).
13. The method of claim 8 , further comprising:
applying a photoresist layer on the hard masking layer;
printing features in the photoresist layer exposing sections of the hard masking layer with photolithography to produce a patterned photoresist layer; and
implanting ions into portions of the hard masking layer not blocked by the patterned photoresist layer; and
etching the hard masking layer.
14. A method for patterning integrated circuit layers, the method comprising:
(a) forming an oxide layer on an integrated circuit (IC) layer to be patterned;
(b) applying a hard masking layer over the formed oxide layer;
(c) coating a photoresist layer onto the hard masking layer;
(d) printing features in the photoresist layer exposing regions of the hard masking layer with photolithography;
(e) selectively implanting regions of the exposed hard masking layer with ion implantation;
(f) etching the hard masking layer exposing sections of the oxide layer, wherein portions of the hard mask layer that are implanted by ion implantation are etched away at a different rate than portions that are not implanted;
(g) removing the photoresist layer from the etched hard masking layer;
(h) performing ion implantation to selected sections of the exposed oxide layer that are not blocked by the etched hard masking layer;
(i) etching the oxide layer, wherein portions of the oxide layer that are implanted by ion implantation are etched away at a different rate than portions that are not implanted;
(j) patterning the integrated circuit layer with the pattern of the etched oxide layer; and
(k) selectively removing the hard masking and oxide layers from the patterned integrated circuit layer.
15. The method of claim 14 , further comprising coupling the integrated circuit layer to a base substrate.
16. The method of claim 14 , wherein said hard masking layer is a material selected from the group of materials consisting of amorphous silicon (a-Si), amorphous carbon (a-C), silicon-carbon-oxide, polycrystalline silicon, silicon nitride (SiNx or Si 3 N 4 ) and silicon oxynitride (SiOxNy) and said oxide layer is a silicon oxide.
17. The method of claim 14 :
wherein the ions used for ion implantation of the hard masking layer or oxide layer are ions of argon (Ar + ); and
wherein regions of the hard masking layer and oxide layer that are implanted with ions are etched away at an increased rate than non-implanted regions.
18. The method of claim 14 :
wherein the ions used for ion implantation of the hard masking layer or oxide layer are ions selected from the group of ions consisting of oxygen and nitrogen; and
wherein regions of the hard masking layer and oxide layer that are implanted with ions are etched away at a reduced rate than non-implanted regions.
19. The method of claim 14 , wherein said ion implantation comprises:
performing ion implantation at positive tilt angle; and
performing ion implantation at negative tilt angle to selectively damage regions of the hard masking layer, wherein regions between photoresist features remain undamaged due to shadowing effects.