Semiconductor packages having redistribution substrate

1. A semiconductor package comprising:

a redistribution substrate;

an interconnect substrate on the redistribution substrate, the interconnect substrate including a hole penetrating thereinside;

a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate;

a metal layer on the semiconductor chip; and

a mold layer in a gap between the semiconductor chip and the interconnect substrate,

wherein the interconnect substrate includes base layer and a conductive member extending through the base layer,

wherein a top surface of the interconnect substrate is positioned at a level lower than that of a top surface of the metal layer,

wherein the mold layer covers the top surface of the interconnect substrate and the top surface of the metal layer,

wherein the metal layer has a width and a planar shape substantially the same as those of the semiconductor chip,

wherein the conductive member comprises:

a lower pad on a bottom surface of the interconnect substrate;

vias and a line pattern in the base layer; and

an upper pad on the top surface of the interconnect substrate;

wherein the upper pad is connected to the lower pad through the vias and the line pattern, and

wherein the upper pad is not aligned with the lower pad in a vertical direction.

2. The semiconductor package of claim 1 , further comprising an adhesive layer connecting and in contact with the semiconductor chip and the metal layer,

wherein the adhesive layer includes a thermosetting polymer or a thermoplastic polymer.

3. The semiconductor package of claim 1 , wherein the redistribution substrate comprises insulative patterns and a conductive pattern between the insulative patterns,

wherein the metal layer and the conductive pattern have a coefficient of thermal expansion greater than that of the semiconductor chip, and

wherein the metal layer has a thermal conductivity greater than that of the semiconductor chip.

4. The semiconductor package of claim 1 , further comprising an upper package on the interconnect substrate and the metal layer,

wherein the upper package is electrically connected to the conductive member.

5. A semiconductor package comprising:

a substrate;

a semiconductor chip on the substrate;

a first metal layer on the semiconductor chip;

an interconnect substrate that is disposed side by side with the semiconductor chip on the substrate and surrounds the semiconductor chip in plan view;

a mold layer in a gap between the semiconductor chip and the interconnect substrate; and

a carbon layer including at least one of carbon nanotube, graphene, and graphite disposed on and contacting a top surface of the first metal layer,

wherein the interconnect substrate includes a base layer and a conductive member extending through the base layer,

wherein the carbon layer has a width and a planar shape substantially the same as a width and a planar shape of the first metal layer, respectively,

wherein the mold layer covers the top surface of the first metal layer and a top surface of the interconnect substrate, and

wherein the width and the planar shape of the first metal layer are substantially the same as those of the semiconductor chip.

6. The semiconductor package of claim 5 ,

wherein the interconnect substrate comprises a hole penetrating thereinside, and

wherein the semiconductor chip is provided in the hole of the interconnect substrate.

7. The semiconductor package of claim 6 , wherein a plurality of semiconductor chips are provided in the hole.

8. The semiconductor package of claim 5 , wherein the conductive member comprises a ground pattern and a signal pattern,

wherein the first metal layer extends onto and is connected to the ground pattern, and

wherein the first metal layer is insulated from the signal pattern.

9. The semiconductor package of claim 8 , further comprising a second metal layer disposed on the semiconductor chip and spaced apart from the first metal layer,

wherein the second metal layer extends onto and is connected to the signal pattern, and

wherein the second metal layer is insulated from the ground pattern.

10. The semiconductor package of claim 5 , further comprising an interposer layer on the interconnect substrate and the semiconductor chip,

wherein the first metal layer is provided in the interposer layer.

11. The semiconductor package of claim 10 , wherein the interposer layer comprises:

an insulation layer including a first surface and a second surface facing each other, wherein the first metal layer is provided on the first surface of the insulation layer;

a metal pattern on the first surface of the insulation layer; and

metal vias that are provided in the insulation layer and respectively disposed on the first metal layer and the metal pattern.

12. The semiconductor package of claim 10 , wherein the interposer layer comprises:

an insulation layer including a first surface and a second surface facing each other, wherein the first metal layer is provided on the first surface of the insulation layer;

a metal pattern on the second surface of the insulation layer; and

metal vias that penetrate the insulation layer and are respectively connected to the first metal layer and the metal pattern.

13. The semiconductor package of claim 5 , wherein the interconnect substrate has a rectangular shape in plan view and is provided in plural on the substrate.

14. A semiconductor package comprising:

a redistribution substrate;

an interconnect substrate on the redistribution substrate, the interconnect substrate including a hole penetrating thereinside;

a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate;

a metal layer on the semiconductor chip; and

a mold layer in a gap between the semiconductor chip and the interconnect substrate,

wherein the interconnect substrate includes base layers and a conductive member extending through the base layers,

wherein a top surface of the interconnect substrate is positioned at a level even with or above that of a top surface of the metal layer,

wherein the mold layer covers the top surface of the metal layer and the top surface of the interconnect substrate, and

wherein the metal layer has a width and a planar shape substantially the same as those of the semiconductor chip.

15. The semiconductor package of claim 14 , further comprising an adhesive layer connecting and in contact with the semiconductor chip and the metal layer, wherein the adhesive layer includes a thermosetting polymer or a thermoplastic polymer.

16. The semiconductor package of claim 14 , wherein the conductive member comprises:

a lower pad on a bottom surface of the interconnect substrate;

a line pattern between the base layers;

vias penetrating the base layers; and

an upper pad on the top surface of the interconnect substrate,

wherein the upper pad is connected to the lower pad through the vias and the line pattern,

wherein the upper pad is not aligned with the lower pad.

17. The semiconductor package of claim 14 , wherein the redistribution substrate comprises insulative patterns and a conductive pattern between the insulative patterns,

wherein the metal layer and the conductive pattern have a coefficient of thermal expansion greater than that of the semiconductor chip, and

wherein the metal layer has a thermal conductivity greater than that of the semiconductor chip.

18. The semiconductor package of claim 1 , wherein the metal layer is in contact with an upper surface of the semiconductor chip.

19. The semiconductor package of claim 1 , further comprising a seed layer formed on and in contact with an upper surface of the semiconductor chip.