Output driving circuit
The output driving circuit include a pull-down driver, an input/output (IO) control logic, a gate control logic, and an inverter. The pull-down driver includes first, second, and third transistors that are sequentially coupled between a pad and a ground node. The IO control logic is configured to receive a clock signal and an enable signal, and transfer a first control signal to the third transistor. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the first transistor. The inverter is configured to invert the enable signal and transfer an inverted enable signal to the gate control logic. Therefore, the reliability of the output driving circuit can be improved.
1. An output driving circuit, comprising:
a pull-down driver including first, second, and third transistors that are sequentially coupled between a pad and a ground node;
an input/output control logic configured to receive a clock signal and an enable signal, and transfer a first control signal to the third transistor;
a gate control logic configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the first transistor; and
an inverter configured to invert the enable signal and transfer an inverted enable signal to the gate control logic, wherein:
a first supply voltage is applied to a gate electrode of the second transistor,
the gate control logic comprises first, second, and third PMOS transistors are sequentially coupled in series between the voltage of the pad and the first supply voltage,
the first supply voltage is applied to a gate electrode of the first PMOS transistor,
the voltage of the pad is applied to a gate electrode of the second PMOS transistor,
the inverted enable signal is applied to a gate electrode of the third PMOS transistor, and
a voltage of bulk regions of the first, second, and third PMOS transistors is outputted as the feedback voltage.
2. The output driving circuit according to claim 1 , further comprising an internal resistor coupled between the pad and the gate control logic.
3. The output driving circuit according to claim 1 , wherein the voltage of the pad is a high voltage having a value of about 1.5 V and greater.
4. The output driving circuit according to claim 1 , wherein the voltage of the pad is a high voltage having a value of about 1.8 V and greater.
5. The output driving circuit according to claim 1 , wherein the voltage of the pad is a high voltage having a value of from about 1.8 V to about 3.3 V.
6. The output driving circuit according to claim 1 , wherein the first, second, and third transistors included in the pull-down driver are NMOS transistors.
7. The output driving circuit according to claim 1 , wherein the first PMOS transistor has a source electrode electrically coupled to the bulk region of the first PMOS transistor.
8. The output driving circuit according to claim 7 , wherein:
the gate control logic further comprises a fourth PMOS transistor coupled between the first supply voltage and the bulk region, and
the voltage of the pad is applied to a gate electrode of the fourth PMOS transistor.
9. The output driving circuit according to claim 8 , wherein the fourth PMOS transistor has a source electrode electrically coupled to a bulk region of the fourth PMOS transistor.
10. The output driving circuit according to claim 7 , wherein:
the gate control logic further comprises a fourth NMOS transistor and a fifth PMOS transistor that are sequentially coupled in series between the bulk region and the first supply voltage,
the first supply voltage is applied to a gate electrode of the fourth NMOS transistor, and
a second control signal is applied to a gate electrode of the fifth PMOS transistor.
11. A semiconductor device having an output driving circuit, said output driving circuit comprising:
a pull-down driver including first, second, and third transistors that are sequentially coupled between a pad and a ground node;
an input/output control logic configured to receive a clock signal and an enable signal, and transfer a first control signal to the third transistor;
a gate control logic configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the first transistor; and
an inverter configured to invert the enable signal and transfer an inverted enable signal to the gate control logic, wherein:
the gate control logic comprises first, second, and third PMOS transistors are sequentially coupled in series between the voltage of the pad and the first supply voltage,
the first supply voltage is applied to a gate electrode of the first PMOS transistor,
the voltage of the pad is applied to a gate electrode of the second PMOS transistor,
the inverted enable signal is applied to a gate electrode of the third PMOS transistor, and
a voltage of bulk regions of the first, second, and third PMOS transistors is outputted as the feedback voltage.
12. The semiconductor device according to claim 11 , wherein said output driving circuit further comprises an internal resistor coupled between the pad and the gate control logic.
13. The semiconductor device according to claim 11 , wherein the voltage of the pad is a high voltage having a value of about 1.5 V and greater.
14. The semiconductor device according to claim 11 , wherein the first, second, and third transistors included in the pull-down driver are NMOS transistors.
15. The semiconductor device according to claim 14 , wherein a first supply voltage is applied to a gate electrode of the second transistor.