ESD protection circuit, driving circuit, pre-driving circuit and IC layout thereof
An IC layout of a pre-driving circuit, comprising: a plurality of type one transistor regions, having a density smaller than a predetermined level; and a type two bulk region, surrounding the type one transistor regions.
1. A pre-driving circuit, comprising:
a voltage level transforming circuit, configured to transform a first input voltage to a first transformed voltage, or to transform a second input voltage to a second transformed voltage, wherein the first input voltage is higher than the second input voltage, and the second transformed voltage is less than the first transformed voltage; and
a driving power enhancement circuit, comprising at least one inverter, wherein the inverter operates at the first input voltage and the second transformed voltage, or operates at the first transformed voltage and the second input voltage.
2. The pre-driving circuit of claim 1 , wherein the voltage level transforming circuit transfers the first input voltage to the first transformed voltage, and the inverter operates at the first transformed voltage and the second input voltage.
3. The pre-driving circuit of claim 2 , further comprising at least one logic gate and at least one inverter which is different from the inverter of the driving power enhancement circuit, wherein the logic gate and the inverter which is different from the inverter of the driving power enhancement circuit are electrically coupled between the voltage level transforming circuit and the driving power enhancement circuit, and operate at the first transformed voltage and the second input voltage.
4. The pre-driving circuit of claim 1 , wherein the voltage level transforming circuit transfers the second input voltage to the second transformed voltage, and the inverter operates at the first input voltage and the second transformed voltage.
5. The pre-driving circuit of claim 4 , further comprising at least one logic gate and at least one inverter which is different from the inverter of the driving power enhancement circuit, wherein the logic gate and the inverter which is different from the inverter of the driving power enhancement circuit are electrically coupled between the voltage level transforming circuit and the driving power enhancement circuit, and operate at the first input voltage and the second transformed voltage.
6. The pre-driving circuit of claim 1 , wherein the driving power enhancement circuit is electrically coupled to a driving circuit, wherein the driving circuit comprises:
a first type one transistor electrically coupled to a second voltage source;
a second type one transistor electrically coupled to the first type one transistor in series, and a control terminal of the second type one transistor is electrically coupled to the first voltage source; and
a first type two transistor electrically coupled between the first voltage source and the second type one transistor.
7. The pre-driving circuit of claim 6 , wherein the first type one transistor and the second type one transistor are NMOSs when the first type two transistor is a PMOS, wherein the first type one transistor and the second type one transistor are PMOSs when the first type two transistor is an NMOS.