Gate dielectric breakdown protection during ESD events
Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.
1. A circuit for protecting an integrated circuit from an electrostatic discharge (ESD) event, the circuit comprising:
a power supply rail;
an input/output pad;
a buffer circuit comprising a first field-effect transistor with a gate coupled to the input/output pad, a source, a gate dielectric layer, and a body;
a second field-effect transistor including a gate, a drain coupled to the body of the first field-effect transistor, and a source selectively coupled to the power supply rail; and
a trigger circuit coupled with the input/output pad and with the gate of the second field-effect transistor, the trigger circuit configured to output a first voltage to the gate of the second field-effect transistor in response to the ESD event at the input/output pad and while the integrated circuit is unpowered,
wherein the second field-effect transistor enters a cutoff condition in response to the first voltage at the gate of the second field-effect transistor so that the second field-effect transistor electrically isolates the body of the first field-effect transistor from the power supply rail.
2. The circuit of claim 1 wherein the trigger circuit is further configured to output a second voltage to the gate of the second field-effect transistor in response to the integrated circuit being powered, and the second field-effect transistor enters a saturated condition in response to the second voltage at the gate of the second field effect transistor so that the body of the first field-effect transistor is coupled to the power supply rail.
3. The circuit of claim 1 further comprising:
a third field-effect transistor including a gate coupled to the trigger circuit, a drain coupled to the source of the first field-effect transistor, and a source coupled to the power supply rail,
wherein the third field-effect transistor is configured to selectively couple the source of the first field-effect transistor to the power supply rail.
4. The circuit of claim 3 further comprising:
a fourth field-effect transistor having a gate coupled with the trigger circuit, a source coupled to the power supply rail, and a drain coupled to the source of the third field-effect transistor.
5. The circuit of claim 4 wherein the trigger circuit is further configured to output a third voltage in response to the ESD event at the input/output pad, the fourth field-effect transistor enters a saturation condition in response to the third voltage so that the gate of the third field-effect transistor is coupled to the power rail.
6. The circuit of claim 3 further comprising:
a drive circuit coupled with the gate of the third field-effect transistor.
7. The circuit of claim 3 wherein the trigger circuit is further configured to output a third voltage to the gate of the fourth field-effect transistor in response to the integrated circuit being powered, and the fourth field-effect transistor enters a cutoff condition in response to third voltage at the gate of the fourth field effect transistor so that the gate of the first field-effect transistor is isolated from the power supply rail.
8. The circuit of claim 1 wherein the second field-effect transistor has a gate dielectric layer that is thicker than the gate dielectric layer of the first field-effect transistor.
9. The circuit of claim 1 wherein the first field-effect transistor and the second field-effect transistor are n-channel field-effect transistors.
10. The circuit of claim 1 wherein the buffer circuit comprises an inverter that includes the first field-effect transistor.
11. A hardware description language (HDL) design structure encoded on a non-transitory machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit for protecting an integrated circuit during an electrostatic discharge (ESD) event, the HDL design structure comprising:
a power supply rail;
an input/output pad;
a buffer circuit comprising a first field-effect transistor with a gate coupled to the input/output pad, a source, a gate dielectric layer, and a body;
a second field-effect transistor including a gate, a drain coupled to the body of the first field-effect transistor, and a source selectively coupled to the power supply rail; and
a trigger circuit coupled with the input/output pad and with the gate of the second field-effect transistor, the trigger circuit configured to output a first voltage to the gate of the second field-effect transistor in response to the ESD event at the input/output pad and while the integrated circuit is unpowered,
wherein the second field-effect transistor enters a cutoff condition in response to the first voltage at the gate of the second field-effect transistor so that the second field-effect transistor electrically isolates the body of the first field-effect transistor from the power supply rail.
12. The HDL design structure of claim 11 wherein the HDL design structure comprises a netlist.
13. The HDL design structure of claim 11 wherein the DHL design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
14. The HDL design structure of claim 11 wherein the HDL design structure resides in a programmable gate array.