Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library
Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.
1. A method comprising:
performing a placement process for a circuit design by assigning physical locations to cells from a cell library to produce a layout using a processor, the layout has continuous linear active areas of the cells adjoining one another, and the cells have different widths perpendicular to the continuous linear active areas;
assigning an alignment context to each of the cells, from previously established alignment contexts, based on how the different widths cause each of the cells to align with adjoining cells using the processor;
retrieving signal delay times for each of the cells from the cell library;
adjusting the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells to produce adjusted delay times for each of the cells using the processor;
performing a timing analysis of the layout using the adjusted delay times for each of the cells using the processor; and
in response to the timing analysis of the layout satisfying timing requirements, adjusting the circuit design based on output results of the timing analysis and providing the circuit design for manufacturing integrated circuits.
2. The method according to claim 1 , each of the alignment contexts reference a different delay multiple that is based on how each of the alignment contexts cause different amounts of strain within the cells.
3. The method according to claim 2 , the adjusting of the signal delay times comprises multiplying the signal delay times by the delay multiple of the assigned alignment context for each cell.
4. The method according to claim 2 , the cells include transistors and the strain changes how quickly the transistors process signals.
5. The method according to claim 1 , the assigning the alignment context comprises comparing the ratio of a width perpendicular to the continuous linear active areas of a first cell to a width perpendicular to the continuous linear active areas of a second cell contacting the first cell, to produce a width-to-width ratio; and
matching the width-to-width ratio to a table to assign one of the alignment context to the cells.
6. The method according to claim 1 , the assigning the alignment context is based on the different widths of adjoining cells on each side of each of the cells.
7. The method according to claim 1 , the cells have transistors that comprise planar and 3D transistors.
8. A method comprising:
receiving a circuit design into a design automation system;
automatically identifying cells in a standard cell library that correspond to components within the circuit design, using a processor of the design automation system;
automatically performing a placement process for the circuit design by assigning physical locations to the cells to produce a layout using the processor, the layout has continuous linear active areas of the cells adjoining one another, and the cells have different widths perpendicular to the continuous linear active areas;
automatically assigning an alignment context to each of the cells, from previously established alignment contexts, based on how the different widths cause each of the cells to align with adjoining cells using the processor;
automatically retrieving signal delay times for each of the cells from the standard cell library using the processor;
automatically adjusting the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells to produce adjusted delay times for each of the cells using the processor;
automatically performing a timing analysis of the layout using the adjusted delay times for each of the cells using the processor;
outputting results of the timing analysis from an interface of the design automation system; and
in response to the timing analysis of the layout satisfying timing requirements, adjusting the circuit design based on output results of the timing analysis and providing the circuit design for manufacturing integrated circuits.
9. The method according to claim 8 , each of the alignment contexts reference a different delay multiple that is based on how each of the alignment contexts cause different amounts of strain within the cells.
10. The method according to claim 9 , the adjusting of the signal delay times comprises multiplying the signal delay times by the delay multiple of the assigned alignment context for each cell.
11. The method according to claim 9 , the cells include transistors and the strain changes how quickly the transistors process signals.
12. The method according to claim 8 , the assigning the alignment context comprises comparing the ratio of a width perpendicular to the continuous linear active areas of a first cell to a width perpendicular to the continuous linear active areas of a second cell contacting the first cell, to produce a width-to-width ratio; and
matching the width-to-width ratio to a table to assign one of the alignment context to the cells.
13. The method according to claim 8 , the assigning the alignment context is based on the different widths of adjoining cells on each side of each of the cells.
14. The method according to claim 8 , the cells have transistors that have gates that run in a direction parallel to the width of the cells.
15. A design automation system comprising:
a processor;
a standard cell library operatively connected to the processor;
an alignment context table operatively connected to the processor; and
an interface operatively connected to the processor,
the processor automatically identifies cells in the standard cell library that correspond to components within a circuit design,
the processor automatically performs a placement process for the circuit design by assigning physical locations to the cells to produce a layout, the layout has continuous linear active areas of the cells adjoining one another, and the cells have different widths perpendicular to the continuous linear active areas,
the processor automatically assigns an alignment context to each of the cells, from previously established alignment contexts in the alignment context table, based on how the different widths cause each of the cells to align with adjoining cells,
the processor automatically retrieves standard signal delay times for each of the cells from the standard cell library,
the processor automatically adjusts the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells to produce adjusted delay times for each of the cells,
the processor automatically performs a timing analysis of the layout using the adjusted delay times for each of the cells,
the interface automatically outputs results of the timing analysis, and
in response to the timing analysis of the layout satisfying timing requirements, the circuit design is adjusted based on output results of the timing analysis and the interface provides the circuit design for manufacturing integrated circuits.
16. The design automation system according to claim 15 , each of the alignment contexts reference a different delay multiple that is based on how each of the alignment contexts cause different amounts of strain within the cells.
17. The design automation system according to claim 16 , the processor adjusts the signal delay times by multiplying the signal delay times by the delay multiple of the assigned alignment context for each cell.
18. The design automation system according to claim 16 , the cells include transistors and the strain changes how quickly the transistors process signals.
19. The design automation system according to claim 15 , the processor assigns the alignment context by:
comparing the ratio of a width perpendicular to the continuous linear active areas of a first cell to a width perpendicular to the continuous linear active areas of a second cell contacting the first cell, to produce a width-to-width ratio; and
matching the width-to-width ratio to a table to assign one of the alignment context to the cells.
20. The design automation system according to claim 15 , the processor assigns the alignment context based on the different widths of adjoining cells on each side of each of the cells.