Flat no-lead packages with electroplated edges
A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.
1. A method of forming packaged semiconductor devices, comprising:
providing a lead frame sheet including a plurality of joined flat no-lead lead frames (lead frames) each having a semiconductor die including bond pads thereon mounted on a die pad of said lead frames with bond wires between said bond pads and terminals of said lead frames, and plastic encapsulation except on a back side of said lead frame sheet to expose a back side of said die pad to provide an exposed thermal die pad and to expose a back side of said terminals;
partial sawing in saw lanes beginning from said back side of said lead frame sheet through said terminals ending with saw lines having a line width terminating within said plastic encapsulation to provide exposed side walls of said terminals and exposed side walls of said plastic encapsulation;
shorting together said exposed thermal pad and said exposed back side of the terminals to form electrically interconnected metal surfaces;
electroplating said electrically interconnected metal surfaces with a stack of plating layers on said back side and on said exposed side walls of said terminals, said stack of plating layers includes nickel, palladium, and gold;
decoupling said interconnected surfaces, and
a second sawing in said saw lanes to finish sawing through said plastic encapsulation to provide singulation to form a plurality of said packaged semiconductor devices.
2. The method of claim 1 , wherein said partial sawing includes mechanical sawing or laser sawing.
3. The method of claim 1 , where said shorting together includes wire bonding bond wires and wherein said decoupling includes using a metal brush for shearing off said bond wires.
4. The method of claim 1 , wherein said lead frames comprise quad-flat no-lead (QFN) or dual-flat no-lead (DFN).
5. The method of claim 1 , wherein said shorting together includes using a metal jig.
6. The method of claim 1 , wherein a sawn width for said second sawing is less than said line width.
7. The method of claim 1 , wherein said exposed thermal pad and said back side of said terminals each include a contact region which lacks said plating layer.
8. The method of claim 1 , wherein said lead frames include copper or a copper alloy.