Memory system performing read of nonvolatile semiconductor memory device
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
1. A memory system comprising:
a nonvolatile semiconductor memory device including a memory cell array including a plurality of blocks, one of the blocks including a plurality of memory cells, and
a control unit configured to set a voltage supplied to the memory cell in a read, wherein the control unit is configured:
to set a first voltage supplied to the memory cell in a first read,
in a case that a second voltage supplied to the memory cell is set in a second read after the first read, to record data related to the second voltage, the second voltage different from the first voltage, and
to set a third voltage supplied to the memory cell based on the recorded data related to the second voltage in a third read after the second read, the third voltage different from the first voltage and the second voltage.
2. The memory system of claim 1 , wherein
in a case that an error is detected after the first read, the control unit is configured to set the second voltage in the second read, and
in a case that the second voltage is set in the second read and an error is not detected after the second read, the control unit is configured to record the data.
3. The memory system of claim 1 , wherein the second voltage is higher or lower than the first voltage.
4. The memory system of claim 1 , wherein a time of the first read is different from a time of the second read.
5. The memory system of claim 4 , wherein the time of the first read is different from the time of the second read by one of changing a precharge voltage of a sense node of the memory cell and changing the number of times of sense.
6. The memory system of claim 4 , wherein a fourth voltage supplied to an unselected word line adjacent to a selected word line in the second read is higher than a fifth voltage supplied to the unselected word line in the first read.
7. The memory system of claim 2 , wherein
in a case that an error is detected after the second read, the control unit is configured to set a fourth voltage supplied to the memory cell in a fourth read, the fourth voltage different from the first voltage and the second voltage, and
in a case that an error is not detected after the fourth read, the control unit is configured to record data related to the fourth voltage.
8. The memory system of claim 7 , wherein the second voltage is higher than the first voltage and the fourth voltage is lower than the first voltage.
9. The memory system of claim 1 , wherein in a case that the second voltage is set in the second read based on a standing time of the nonvolatile semiconductor memory device, the control unit is configured to record the data related to the second voltage.
10. The memory system of claim 1 , wherein in a case that the second voltage is set in the second read based on at least one of a write count, an erase count, and a read count, the control unit is configured to record the data related to the second voltage.