Memory system performing read operation using read voltage
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
1 . A memory system comprising:
a nonvolatile semiconductor memory device including a plurality of memory cells, and
a control circuit configured to:
send a first command, to the nonvolatile semiconductor memory device, to read data stored in the memory cells using a first voltage corresponding to a voltage between a first threshold voltage and a second threshold voltage, and
send a second command, to the nonvolatile semiconductor memory device, to read the data using a second voltage that is lower than the first voltage and corresponding to the voltage between the first threshold voltage and the second threshold voltage, after a first time has elapsed from a previous access to the memory cells.
2 . The memory system of claim 1 , wherein the control circuit is configured to send a third command, to the nonvolatile semiconductor memory device, to read the data using a third voltage that is higher than the first voltage, after a second time has elapsed from the previous access to the memory cells, the second time being shorter than the first time.
3 . The memory system of claim 1 , wherein in a case where an error is detected on data read in a read operation according to the second command, the control circuit is configured to execute a refresh operation on the data read in the read operation according to the second command.
4 . The memory system of claim 1 , wherein the control circuit is configured to perform an error correction on data read in a read operation according to the second command.
5 . The memory system of claim 1 , wherein a value of the second voltage vary according to a temperature in the memory system.
6 . The memory system of claim 1 , wherein in a case where an error is detected on data read in a read operation according to the first command, the control circuit is configured to send a fourth command, to the nonvolatile semiconductor memory device, to read the data using a fourth voltage that is lower than the first voltage.
7 . The memory system of claim 1 , wherein each of the plurality of memory cells is configured to store data of three or more values.
8 . The memory system of claim 1 , wherein the nonvolatile semiconductor memory includes a NAND flash memory.
9 . The memory system of claim 1 , further comprising a memory configured to store a firmware for an operation of the control circuit.
10 . The memory system of claim 9 , wherein the memory includes a DRAM.
11 . A memory system comprising:
a nonvolatile semiconductor memory device including a plurality of memory cells, and
a control circuit configured to:
send a first command, to the nonvolatile semiconductor memory device, to read data stored in the memory cells using a first voltage corresponding to a voltage between a first threshold voltage and a second threshold voltage, and
send a second command, to the nonvolatile semiconductor memory device, to read the data using a second voltage that is higher than the first voltage and corresponding to the voltage between the first threshold voltage and the second threshold voltage, after a first time has elapsed from a previous access to the memory cells.
12 . The memory system of claim 11 , wherein in a case where an error is detected on data read in a read operation according to the second command, the control circuit is configured to execute a refresh operation on the data read in the read operation according to the second command.
13 . The memory system of claim 11 , wherein the control circuit is configured to perform an error correction on data read in a read operation according to the second command.
14 . The memory system of claim 11 , wherein a value of the second voltage vary according to a temperature in the memory system.
15 . The memory system of claim 11 , wherein in a case where an error is detected on data read in a read operation according to the first command, the control circuit is configured to send a third command, to the nonvolatile semiconductor memory device, to read the data using a third voltage that is lower than the first voltage.
16 . The memory system of claim 11 , wherein in a case where an error is detected on data read in a read operation according to the first command, the control circuit is configured to send a fourth command, to the nonvolatile semiconductor memory device, to read the data using a fourth voltage that is higher than the first voltage.
17 . The memory system of claim 11 , wherein each of the plurality of memory cells is configured to store data of three or more values.
18 . The memory system of claim 11 , wherein the nonvolatile semiconductor memory includes a NAND flash memory.
19 . The memory system of claim 11 , further comprising a memory configured to store a firmware for an operation of the control circuit.
20 . The memory system of claim 19 , wherein the memory includes a DRAM.