Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer
A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.
1. A wafer-level chip-scale package comprising:
a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via;
a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate; and
a seal ring including metal disposed in the body and having an upper end directly bonded to the piezoelectric substrate.
2. The wafer-level chip-scale package of claim 1 further comprising a metal roof encapsulated in a dielectric and disposed on an upper surface of the body below the cavity.
3. The wafer-level chip-scale package of claim 2 further comprising metal standoffs disposed between the dielectric and the piezoelectric substrate.
4. The wafer-level chip-scale package of claim 1 further comprising a metal standoff disposed between one of the upper end of the conductive via and the piezoelectric substrate and the upper end of the seal ring and the piezoelectric substrate.
5. The wafer-level chip-scale package of claim 1 wherein the seal ring surrounds the cavity and hermetically seals the cavity.
6. The wafer-level chip-scale package of claim 1 further comprising a dielectric layer disposed on walls of the cavity and hermetically sealing the cavity.
7. The wafer-level chip-scale package of claim 1 further comprising interdigital (IDT) electrodes of an acoustic wave filter disposed on the piezoelectric substrate within the cavity.
8. The wafer-level chip-scale package of claim 1 further comprising a passive device disposed within the body.
9. The wafer-level chip-scale package of claim 8 wherein the passive device includes an inductor.
10. The wafer-level chip-scale package of claim 1 wherein the body includes polyimide.
11. The wafer-level chip-scale package of claim 10 wherein the body includes two layers of polymer and a dielectric layer disposed between the two layers of polymer.
12. The wafer-level chip-scale package of claim 1 further comprising a first polymer standoff disposed between the body and the piezoelectric substrate.
13. The wafer-level chip-scale package of claim 12 wherein the first polymer standoff defines a first lateral end of the cavity and a second polymer standoff disposed between the body and the piezoelectric substrate defines a second lateral end of the cavity.
14. The wafer-level chip-scale package of claim 1 further comprising a metal roof disposed within the body below the cavity.
15. The wafer-level chip-scale package of claim 1 further comprising a metal roof disposed on an upper surface of the body and defining a lower surface of the cavity.
16. The wafer-level chip-scale package of claim 15 further comprising metal standoffs disposed between the metal roof and the piezoelectric substrate.
17. The wafer-level chip-scale package of claim 1 included in an electronic device module.
18. The wafer-level chip-scale package of claim 17 wherein the electronic device module is a radio frequency (RF) device module.
19. The wafer-level chip-scale package of claim 18 wherein the electronic device module is included in a duplexer.
20. The wafer-level chip-scale package of claim 18 included in an electronic device.
21. The wafer-level chip-scale package of claim 20 wherein the electronic device is an RF device.
22. A wafer-level chip-scale package comprising:
a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via;
a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate;
a metal roof disposed on an upper surface of the body and defining a lower surface of the cavity; and
metal standoffs disposed between the metal roof and the piezoelectric substrate.
23. A wafer-level chip-scale package comprising:
a polymeric body including polyimide having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via, the body including two layers of polymer and a dielectric layer disposed between the two layers of polymer; and
a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate.
24. A wafer-level chip-scale package comprising:
a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via;
a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate;
a metal roof encapsulated in a dielectric and disposed on an upper surface of the body below the cavity; and
metal standoffs disposed between the dielectric and the piezoelectric substrate.