IP Library › Granted Patent US 10,381,309
Granted Patent B2
US 10,381,309 · App. 15/965,980 · Granted Aug 13, 2019

Package structure having connecting module

Inventors: Chuei-Tang Wang (Taichung, TW); Chung-Hao Tsai (Changhua County, TW); Chen-Hua Yu (Hsinchu, TW); Chun-Lin Lu (Hsinchu, TW); Chao-Wen Shih (Hsinchu County, TW); Han-Ping Pu (Taichung, TW); Kai-Chiang Wu (Hsinchu, TW); Albert Wan (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L23/5384H01L23/28H01L23/49816H01L25/0657H01L25/50H01L2224/18
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Quick Facts
Patent No.
US 10,381,309
App. No.
15/965,980
Granted
Aug 13, 2019
Kind
B2
Abstract

A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer. The at least one connecting module connects to the first redistribution layer and is electrically connected to the at least one semiconductor chip through the first redistribution layer, wherein the at least one connecting module comprises a plurality of pins, and the at least one connecting module is mounted onto the first redistribution layer by the protection layer and is accessibly exposed by the protection layer.

Claims (21)

1. A package structure, comprising:

a first redistribution layer and a second redistribution layer;

at least one semiconductor chip, located between and electrically connected to the first redistribution layer and the second redistribution layer;

an insulating encapsulation, encapsulating the at least one semiconductor chip;

a protection layer, disposed on and partially covering the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer; and

at least one connecting module, connecting to the first redistribution layer and electrically connected to the at least one semiconductor chip through the first redistribution layer, wherein the at least one connecting module comprises a circuit board and a plurality of pins connected thereto, and the at least one connecting module is mounted onto the first redistribution layer by the protection layer and is accessibly exposed by the protection layer.

2. The package structure of claim 1 , further comprising:

through vias, located between and electrically connected to the first redistribution layer and the second redistribution layer and encapsulated in the insulating encapsulation, wherein the through vias are disposed aside of a location of the at least one semiconductor chip.

3. The package structure of claim 1 , further comprising:

warpage control elements, located between the first redistribution layer and the second redistribution layer and encapsulated in the insulating encapsulation, wherein a first group of the warpage control elements are disposed aside of a location of the at least one semiconductor chip, and a second group of the warpage control elements are disposed between the second redistribution layer and the at least one semiconductor chip.

4. The package structure of claim 1 , further comprising:

at least one first passive element, located at a side of the second redistribution layer, wherein the at least one first passive element is mechanically connected to one of the first redistribution layer and the second redistribution layer.

5. The package structure of claim 4 , further comprising:

at least one second passive element, located at a side of the second redistribution layer, wherein the at least one second passive element is electrically connected to the first redistribution layer and at least partially encapsulated in the protection layer.

6. The package structure of claim 1 , further comprising:

first antenna elements, located over the second redistribution layer; and

an encapsulant, located between the first antenna elements and the second redistribution layer, wherein the second redistribution layer is located between the encapsulant and the at least one semiconductor chip, and a portion of the second redistribution layer is electrically coupled with the first antenna elements.

7. The package structure of claim 6 , further comprising:

first air cavities, formed within the encapsulant, wherein a location of each of the first air cavities is overlapped with a location of a respective one of the first antennas in the vertical projection on the second redistribution layer.

8. The package structure of claim 7 , further comprising:

second antenna elements, located in the first air cavities respectively, wherein the second antenna elements are electrically coupled with the first antenna elements, respectively.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2018
From: WANG, CHUEI-TANG; TSAI, CHUNG-HAO; YU, CHEN-HUA; LU, CHUN-LIN; SHIH, CHAO-WEN; PU, HAN-PING; WU, KAI-CHIANG; WAN, ALBERT
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 046546/0012 →
Continuity (2)
Provisional Application 62589527 · Nov 21, 2017
Related Publication 20190157206A1 · May 23, 2019
Cited By (1)
US 12,322,688