Low resistance source drain contact formation
Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×10 20 at./cm 3 . Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.
1. A device, comprising:
a p-type transistor comprising source and drain regions interconnected by a channel region, and at least one gate configured to regulate current flow through the channel region;
a dielectric over the p-type transistor;
contact trenches present in the dielectric over, and extending down to, the source and drain regions;
an epitaxial material within the contact trenches; and
a crystalline gallium-doped layer on the epitaxial material having a homogenous gallium (Ga) concentration of from about 6×10 20 at./cm 3 to about 8×10 21 at./cm 3 , and ranges therebetween, whereby a layered contact structure is provided comprising three distinct regions including: i) a first region comprising the crystalline gallium-doped layer, ii) a second region, beneath the crystalline gallium-doped layer, comprising the epitaxial material, and iii) a third region, beneath the epitaxial material, comprising the source and drain regions, wherein the first region, the second region and third region each comprises a germanium-containing semiconductor with the first region and the second region having a higher percentage of germanium than the third region, and wherein the first region has the homogenous gallium concentration of from about 6×10 20 at./cm 3 to about 8×10 21 at./cm 3 , and ranges therebetween, and wherein the first region comprising the crystalline gallium-doped layer is directly in contact with the third region comprising the source and drain regions.
2. The device of claim 1 , wherein the source and drain regions comprise boron-doped silicon germanium Si 1-x Ge x :B.
3. The device of claim 2 , wherein the crystalline gallium-doped layer comprises gallium (Ga) and boron (B) doped silicon germanium (SiGe) (SiGe y :Ga:B).
4. The device of claim 3 , wherein the epitaxial material comprises boron-doped silicon germanium SiGe y :B.
5. The device of claim 4 , wherein x<y<1.
6. The device of claim 5 , wherein 0≤x≤0.75.
7. The device of claim 2 , wherein the epitaxial material comprises boron-doped germanium.
8. The device of claim 2 , further comprising:
a metal silicide on the crystalline gallium-doped layer.
9. The device of claim 8 , further comprising:
a contact metal filling the contact trenches.
10. The device of claim 9 , wherein the contact metal comprises a metal selected from the group consisting of tungsten, cobalt, aluminum, and combinations thereof.
11. A device, comprising:
a p-type transistor comprising source and drain regions interconnected by a channel region, and at least one gate configured to regulate current flow through the channel region;
a dielectric over the p-type transistor;
contact trenches present in the dielectric over, and extending down to, the source and drain regions;
an epitaxial material within the contact trenches; and
a crystalline gallium-doped layer in direct contact with the source and drain regions, wherein the crystalline gallium-doped layer has a homogenous gallium (Ga) concentration of greater than about 5×10 20 at./cm 3 , whereby a layered contact structure is provided comprising three distinct regions including: i) a first region comprising the crystalline gallium-doped layer, ii) a second region, beneath the crystalline gallium-doped layer, comprising the epitaxial material, and iii) a third region, beneath the epitaxial material, comprising the source and drain regions, wherein the first region, the second region and third region each comprises a germanium-containing semiconductor with the first region and the second region having a higher percentage of germanium than the third region, and wherein the first region has the homogenous gallium concentration of greater than about 5×10 20 at./cm 3 , and wherein the first region comprising the crystalline gallium-doped layer is directly in contact with the third region comprising the source and drain regions.
12. The device of claim 11 , wherein the source and drain regions comprise boron-doped silicon germanium Si 1-x Ge x :B.
13. The device of claim 12 , wherein the crystalline gallium-doped layer comprises gallium (Ga) and boron (B) doped silicon germanium (SiGe) (SiGe y :Ga:B).
14. The device of claim 13 , wherein x<y<1.
15. The device of claim 14 , wherein 0≤x≤0.75.
16. The device of claim 11 , further comprising:
a metal silicide on the crystalline gallium-doped layer.
17. The device of claim 16 , further comprising:
a contact metal filling the contact trenches.
18. The device of claim 17 , wherein the contact metal comprises a metal selected from the group consisting of tungsten, cobalt, aluminum, and combinations thereof.
19. The device of claim 11 , wherein the crystalline gallium-doped layer comprises gallium (Ga) and boron (B) doped germanium (Ge) (Ge:Ga:B).