Semiconductor memory device having bonding metal between an array chip and a circuit chip
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
1. A semiconductor memory device comprising:
a circuit chip including
a semiconductor substrate,
MOSFETs formed on the semiconductor substrate, and
a first interconnection layer electrically connected to one of the MOSFETs;
an array chip stuck on the circuit chip, the array chip including
a plurality of stacked electrode layers comprising word lines,
a semiconductor body extending in a stacking direction of the stacked electrode layers,
a charge storage portion provided between the semiconductor body and at least one of the electrode layers, and
a bit line electrically connected to a lower end of the semiconductor body; and
a first bonding metal disposed in a sticking boundary of the array chip and the circuit chip to electrically connect the bit line to the first interconnection layer.
2. The device according to claim 1 , wherein
end portions of the electrode layers are formed in a step shape,
the circuit chip further includes a second interconnection layer electrically connected to one of the MOSFETs,
the array chip further includes a word interconnection layer electrically connected to one of the end portions of the electrode layers, and
the device further includes a second bonding metal disposed in the sticking boundary of the array chip and the circuit chip, to electrically connect the word interconnection layer to the second interconnection layer.
3. The device according to claim 2 , wherein
the second bonding metal is disposed between the word interconnection layer and the second interconnection layer.
4. The device according to claim 2 , wherein
the array chip further includes a pad, and
the device further includes an external connection electrode extending to an upper surface of the pad.
5. The device according to claim 4 , wherein
the pad is provided in a same layer as word interconnection layer and is formed of a same material as the word interconnection layers.
6. The device according to claim 4 , wherein
the pad is provided in a same layer as the first select gate interconnection layer and is formed of a same material as the first select gate interconnection layer.
7. The device according to claim 1 , wherein
the circuit chip further includes a third interconnection layer electrically connected to one of the MOSFETs,
the array chip further includes a first layer comprising a source line, provided above an upper most layer of the electrode layers and electrically connected to an upper end of the semiconductor body,
the device further includes a third bonding metal disposed in a sticking boundary of the array chip and the circuit chip to electrically connect the first layer to the third interconnection layer.
8. The device according to claim 1 , wherein
the circuit chip further includes a fourth interconnection layer electrically connected to one of the MOSFETs,
the array chip further includes a first select gate layer provided between a lower most layer of the electrode layers and the bit line, and a first select gate interconnection layer electrically connected to the first select gate layer,
the device further includes a fourth bonding metal disposed in a sticking boundary of the array chip and the circuit chip to electrically connect the first select gate interconnection layer to the fourth interconnection layer.
9. The device according to claim 1 , wherein
the circuit chip further includes a fifth interconnection layer provided above the MOSFETs and electrically connected to one of the MOSFETs,
the array chip further includes a second select gate layer provided above an upper most layer of the electrode layers, and a second select gate interconnection layer electrically connected to the second select gate layer,
the device further including a fifth bonding metal disposed in a sticking boundary of the array chip and the circuit chip to electrically connect the second select gate interconnection layer to the fifth interconnection layer.
10. The device according to claim 1 , wherein
the first bonding metal is disposed between the bit line and the first interconnection layer.
11. The device according to claim 1 , further comprising an insulating material provided around the first bonding metal.
12. The device according to claim 1 , wherein the semiconductor substrate has thickness of 10 to 20 μm.
13. The device according to claim 1 , wherein
the first bonding metal is a copper or a copper alloy.
14. A semiconductor memory device comprising:
a circuit chip including
a semiconductor substrate,
MOSFETs formed on the semiconductor substrate, and
a second circuit-side interconnection layer electrically connected to one of the MOSFETs;
an array chip stuck on the circuit chip, the array chip including
a plurality of stacked electrode layers comprising word lines,
a semiconductor body extending in a stacking direction of the electrode layers in the electrode layers, and
a charge storage portion provided between the semiconductor body and at least one of the electrode layers; and
a second bonding metal disposed in a sticking boundary of the array chip and the circuit chip, wherein
end portions of the electrode layers are formed in a step shape,
the array chip further includes a word interconnection layer electrically connected to one of the electrode layers in the step structure section, and
the second bonding metal is disposed to electrically connect the word interconnection layer to the second circuit-side interconnection layer.
15. A semiconductor memory device comprising:
a circuit chip including
a semiconductor substrate,
MOSFETs formed on the semiconductor substrate, and
a third circuit-side interconnection layer electrically connected to one of the MOSFETs;
an array chip stuck on the circuit chip, the array chip including
a plurality of stacked electrode layers comprising word lines,
a semiconductor body extending in a stacking direction of the electrode layers in the electrode layers,
a charge storage portion provided between the semiconductor body and at least one of the electrode layers, and
a first layer comprising a source line, provided above an upper most layer of the electrode layers and electrically connected to an upper end of the semiconductor body; and
a third bonding metal disposed in a sticking boundary of the array chip and the circuit chip, the third bonding metal being disposed to electrically connect the first layer to the third circuit-side interconnection layer.
16. A semiconductor memory device comprising:
a circuit chip including
a semiconductor substrate,
MOSFETs formed on the semiconductor substrate, and
a first circuit-side interconnection layer electrically connected to one of the MOSFETs;
an array chip stuck on the circuit chip, the array chip including
a plurality of stacked electrode layers comprising word lines,
a semiconductor body extending in a stacking direction of the electrode layers in the electrode layers, and
a charge storage portion provided between the semiconductor body and at least one of the electrode layers; and
a first bonding metal disposed in a sticking boundary of the array chip and the circuit chip, the first bonding metal being disposed to electrically connect the semiconductor body to the first circuit-side interconnection layer, wherein
the circuit chip except for the semiconductor substrate is thinner than the array chip.