Semiconductor device including air gaps and method for fabricating the same
Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
1. A semiconductor device, comprising:
a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug;
a spacer structure having air gaps formed on sidewalls of the first contact plug and on sidewalls of the bit line;
a plug isolation layer formed between the plurality of bit line structures, the plug isolation layer including an opening;
a second contact plug formed in the opening;
a memory element formed over the second contact plug; and
a contact hole formed on the substrate,
wherein the first contact plug and the air gaps are formed in the contact hole,
wherein the air gaps extending from between the first contact plug and the second contact plug to between the bit line and the second contact plug, and
wherein a bottom surface of the air gaps has a lower level than the top surface of the substrate, and
wherein the air gaps which extend from between the first contact plug and the second contact plug directly contact the second contact plug.
2. The semiconductor device of claim 1 , wherein the spacer structure comprises:
a first spacer structure formed between the first contact plug and the second contact plug; and
a second spacer structure formed between the bit line and the second contact plug.
3. The semiconductor device of claim 2 , wherein:
the first spacer structure includes first spacers formed on both sidewalls of the first contact plug, and
the air gaps are formed between the first spacers and the second contact plug.
4. The semiconductor device of claim 2 , wherein:
the second spacer structure includes first spacers formed on both sidewalls of the bit line and second spacers formed on sidewalls of the first spacers, and
the air gaps are formed between the first spacers and the second spacers.
5. The semiconductor device of claim 4 , wherein the first spacers on one sidewall of the bit line has a different height than the first spacers on another sidewall of the bit line, and
the second spacers on the one sidewall of the bit line has a different height than the second spacers on the another sidewall of the bit line.
6. The semiconductor device of claim 5 , wherein:
the first spacers and the second spacers on the one sidewall of the bit line define an opening of a first air gap of the air gaps, and
the first spacers and the second spacers on the another sidewall of the bit line cap a second air gap of the air gaps.
7. The semiconductor device of claim 4 , further comprising:
a third spacer contacting a corresponding second spacer, of the second spacers, and surrounding the second contact plug.
8. The semiconductor device of claim 1 , wherein the air gap extends in parallel to the sidewalls of the bit line.
9. The semiconductor device of claim 1 , wherein the second contact plug comprises:
a silicon plug adjacent to the first contact plug;
a first metal plug adjacent to the bit line and formed over the silicon plug; and
an ohmic contact layer formed between the silicon plug and the first metal plug.
10. The semiconductor device of claim 1 , further comprising:
a third contact plug between the second contact plug and the memory element, wherein the third contact plug overlaps the second contact plug, the air gap, and the bit line structure.